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features bluecore ? CSR8670? bga bluetooth ? v3.0 specification fully qualified software bluetooth v4.0 specification compliant hardware radio includes integrated balun and rf performance of 10dbm transmit power and -90dbm receive sensitivity 80mhz risc mcu and 80mips kalimba dsp 16mb internal flash memory (64-bit wide, 45ns); optional support for 64mb of external spi flash stereo codec with 2 channels of adc and up to 6 microphone inputs (includes bias generators and digital microphone support) support for csr's lates t cvc technology for narrow-band and wideband voice connections including wind noise reduction audio interfaces: i2s, pcm and spdif serial interfaces: uar t, usb 2.0 full-speed, master and slave bit-se rialiser (i2c and spi) integrated dual switch-mode regulators, linear regulators and battery charger 3 hardware led controlle rs (for rgb) and ability to drive lcd segment display directly support for up to 6 capaci tive touch sensor inputs 6.5 x 6.5 x 1mm, 0.5mm pitch 112?ball vfbga green (rohs compliant and no antimony or halogenated flame retardants) low-power solution for dsp intensive audio applications production information CSR8670c issue 2 2. 4ghz radio + balun i/o bt_rf ram baseband mcu kalimba dsp flash xtal serial flash external memory uart/usb pio audio in / out pcm/i 2 s/ spdif spi /i 2 c led /po audio interface capacitive sense clock generation general description the bluecore ? CSR8670? bga consumer audio platform for wired and wireless applications integrates an ultra-low-power dsp and application processor with embedded flash memory, a high-performance stereo codec, a power m anagement subsystem, led and lcd drivers and capacitive touch sensor inputs in a soc ic. the dual-core architecture with flash memory enables manufacturers to easily differentiate their products with new features without extending development cycles. csr's popular bluecore5-multimedia ? platform is software-portable to the bluecore ? CSR8670? bga, with easy migration of a broad range of solutions from csr's extension partners. this migration enables rapid time-to-market deployment of a broad range of consumer electronics products. the enhanced kalimba dsp coprocessor with 80mips supports enhanced audio and dsp applications. applications home entertainment ecosystem tvs smart remote controllers wired or wireless soundbars wired or wireless speakers and headphones tablets / pcs / mobile connectivity wearable audio (on-the-go) wearable audio with sensors (health and well- being applications) wired or wireless stereo headphones for music/ gaming/multimedia content wired or wireless speakers wired or wireless speakerphones mono headsets for voice the audio codec supports 2 adc channels, up to 6 microphone inputs, stereo output and a variety of audio standards. see csr glossary at www.csrsupport.com . production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 1 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
device details bluetooth radio on-chip balun (50 impedance in tx and rx modes) no external trimming is required in production bluetooth v3.0 specification compliant bluetooth transmitter 10dbm rf transmit power with level control from on-chip 6-bit dac over a dynamic range >30db class 1, class 2 and class 3 support without the need for an external power amplifier or tx/rx switch bluetooth receiver receiver sensitivity of -90dbm integrated channel filters digital demodulator for improved sensitivity and co- channel rejection real-time digitised rss i available to application fast agc for enhanced dynamic range channel classification for afh bluetooth synthesiser fully integrated synthesiser requires no external vco, varactor diode, resonator or loop filter compatible with crystals 19.2mhz to 42mhz or an external clock 19.2mhz to 42mhz accepts 19.2, 19.44, 19.68, 19.8 and 38.4mhz tcxo frequencies for gsm and cdm a devices with sinusoidal or logic level signals kalimba dsp enhanced kalimba dsp coprocessor, 80mips, 24?bit fixed point core 2 single-cycle macs; 24 x 24-bit multiply and 56-bit accumulator 32-bit instruction word, dual 24-bit data memory 12k x 32-bit program ram inc luding 1k instruction cache for executing out of internal flash 32k x 24-bit + 32k x 24-bit 2-bank data ram audio interfaces audio codec with 2 high-quality dedicated adcs 2 microphone bias generators and up to 2 analogue microphone inputs up to 6 digital microphone (mems) inputs g.722 compatible, includes improved digital fir filter path for stop-band attenuation required for g.722 compliance enhanced side-tone gain control supported sample rates of 8, 11.025, 16, 22.05, 32, 44.1, 48 and 96khz (dac only) baseband and software 16mb internal flash memory protection unit supporting accelerated vm 56kb internal ram, enables full-speed data transfer, mixed voice/data and full piconet support logic for forward error correction, header error control, access code correlation, crc, demodulation, encryption bit stream generation, whitening and transmit pulse shaping transcoders for a-law, -law and linear voice via pcm and a-law, -law and cvsd voice over air physical interfaces uart interface usb 2.0 interface (full-speed) master and slave bit-serialiser (i2c and spi) up to 29 pios, i.e. 14 general purpose pios and unused digital interfaces are available as pios spi debug and programming interface with read access disable locking pcm, i2s and spdif interfaces dual/quad external serial flash memory interface 3 led drivers (includes rg b) with pwm flasher on sleep clock support for up to 6 capacitive touch sensor inputs integrated power control and regulation 2 high-efficiency switch-mode regulators with 1.8v and 1.35v outputs from battery supply 3.3v usb pad supply linear regulator low-voltage linear regulator fo r internal digital supply with 0.80v to 1.25v output low-voltage linear regulator f or internal analogue supply with 1.35v output power-on-reset detects low supply voltage power management includes digital shutdown and wake- up commands with an integrated low-power oscillator for ultra-low power park/sniff/hold mode battery charger lithium ion / lithium polymer battery charger with instant- on fast charging support up to 200ma with no external components higher charge currents using external pass device supports usb charge enumeration charger pre-calibrated by csr pse compliance: design to jis-c 8712/8714 (batteries) testing based on ieee 1725 auxiliary features customer application space available crystal oscillator with built-in digital trimming clock request output to control external clock auxiliary adc and dac available to applications package option 6.5 x 6.5 x 1mm, 0.5mm pitch 112?ball vfbga production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 2 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
functional block diagram g-tw-0005372.7.2 memory management unit bluetooth modem 80mhz dsp i 2 c/spi master /slave 16 pio spi (debug) uart 4 mbps system ram serial quad i/o flash (sqif) interface dma ports dma ports pcm / i 2 s /spdif eflash pio spi_debug serial flash/ram i 2 c mic_ln uart 80mhz mcu spkr_ln audio interface mic bias mic_bias_b mic_bias_a usb v2.0 full-speed usb 3. 3v mic bias 6x mems mic digit al mi cs spi?lock /dfu encrypt vm accelerator (mpu ) lcd segment driver pmu interface and bist engine led pwm control and output pm dm1 dm2 rgb digital audio 1. 35v switch- mode regulator bypass ldo smp_vbat lxl_1v8 li-ion charger vchg smps_3v3 1.8v switch- mode regulator lx_1v35 smps_1v8_sense vout_3v3 voltage / temperature monitor bt_rf cap_sense[0] clock generation analogue test aux adc xtal aio[1:0] capacitive touch controller cap_sense[1] cap_sense[2] cap_sense[3] cap_sense[4] cap_sense[5] mic_lp mic_rn mic_rp spkr_lp spkr_rn spkr_rp sense sense bluetooth baseband bluetooth radio and balun tx rx high-quality adc high-quality adc high-quality dac high-quality dac 1. 35v low-voltage vdd_aux linear regulator 1.35v low-voltage vdd_ana linear regulator 0. 85v to 1.2v low-voltage vdd_dig linear regulator dma ports vdd_aux sense vdd_ana sense vdd_bt_radio vdd_dig_eflash sense ch_ext switch smps_1v35_sense sense vbat external connection external connection vdd_aux_1v8 vregin_dig production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 3 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
document history revision date change reason 1 01 apr 11 original publication of this document. 2 30 jun 11 production information added. if you have any comments about this document, email comments@csr.com giving number, title and section with your feedback. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 4 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
status information the status of this data sheet is production information . csr product data sheets progress according to the following for mat: advance information information for designers concerning csr product in development . all values specified are the target values of the design. minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. all detailed specifications including pinouts and electrical sp ecifications may be changed by csr without notice. pre-production information pinout and mechanical dimension specifications finalised. all v alues specified are the target values of the design. minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. all electrical specifications may be changed by csr without not ice. production information final data sheet including the guaranteed minimum and maximum l imits for the electrical specifications. production data sheets supersede all previous document versions . life support policy and use in safety-critical applications csr's products are not authorised for use in life-support or sa fety-critical applic ations. use in suc h applications is done at the sole discre tion of the cu stomer. csr wi ll not warra nt the use of its devices in such applications. csr green semiconductor pro ducts and rohs compliance CSR8670 bga devices meet the requirements of directive 2002/95/ ec of the european parliament and of the council on the restri ction of hazardous substance (rohs). CSR8670 bga devices are also free from halogenated or antimony trioxide-based flame retardants and other hazardous chemicals. for more information, see csr's environmental compliance statement for csr green semiconductor products . trademarks, patents and licences unless otherwise stated, words and logos marked with ? or ? are trademarks registered o r owned by csr plc or its affiliates. bluetooth ? and the bluetooth ? logos are trademarks owned by bluetooth ? sig, inc. and licensed to csr. other products, services and names used in this document m ay have been trademarked by their respective owners. the publication of this information does not imply that any lic ense is granted under any patent or other rights owned by csr plc and/or its affiliates. csr reserves the right to make technical changes to its product s as part of its development programme. while every care has b een taken to ensure the accuracy of the c ontents of this document, csr cannot accept responsibi lity for any errors. refer to www.csrsupport.com for compliance and conformance to standards information. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 5 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
contents device details ................................................ ............................................................... .................................. 2 functional block diagram ..................................... ............................................................... .......................... 3 1 package information .......................................... ............................................................... ............................ 12 1.1 pinout diagram ............................................. ............................................................... ........................ 12 1.2 device terminal functions .................................. ............................................................... ................. 12 1.3 package dimensions ......................................... ............................................................... ................... 19 1.4 pcb design and assembly con siderations ..................... ............................................................... ..... 20 1.5 typical solder reflow pr ofile .............................. ............................................................... .................. 20 2 bluetooth modem .............................................. ............................................................... ............................. 21 2.1 rf ports ................................................... ............................................................... ............................. 21 2.1.1 bt_rf .................................................... ............................................................... ................. 21 2.2 rf receiver ................................................ ............................................................... .......................... 21 2.2.1 low noise amplifier ...................................... ............................................................... .......... 21 2.2.2 rssi analogue to digital converter ....................... ............................................................... . 21 2.3 rf transmitter ............................................. ............................................................... ......................... 22 2.3.1 iq modulator ............................................. ............................................................... .............. 22 2.3.2 power amplifier .......................................... ............................................................... ............. 22 2.4 bluetooth radio synthesiser ................................ ............................................................... ................ 22 2.5 baseband ................................................... ............................................................... ........................... 22 2.5.1 burst mode cont roller .................................... ............................................................... ......... 22 2.5.2 physical layer hardware engine ........................... ............................................................... . 22 3 clock generation ............................................. ............................................................... .............................. 23 3.1 clock architectu re ......................................... ............................................................... ........................ 23 3.2 input frequencies and ps key settings ...................... ............................................................... ......... 23 3.3 external reference clock ................................... ............................................................... .................. 24 3.3.1 input: xtal_in ........................................... ............................................................... ............. 24 3.3.2 xtal_in impedance in ext ernal mode ....................... ........................................................... 24 3.3.3 clock timing accuracy .................................... ............................................................... ........ 24 3.4 crystal oscillator: xtal_in and xtal_out ................... ............................................................... ..... 25 3.4.1 crystal calibration ...................................... ............................................................... ............. 25 3.4.2 crystal specification .................................... ............................................................... ............ 26 4 bluetooth stack microcontroller .............................. ............................................................... ....................... 27 4.1 vm accelerator ............................................. ............................................................... ........................ 27 5 kalimba dsp .................................................. ............................................................... ............................... 28 6 memory interface and management .............................. ............................................................... ................ 29 6.1 memory management unit ..................................... ............................................................... .............. 29 6.2 system ram ................................................. ............................................................... ........................ 29 6.3 kalimba dsp ram ............................................ ............................................................... ................... 29 6.4 eflash memory (16mb) ....................................... ............................................................... .................. 29 6.5 serial quad i/o flash interface (sqif) ..................... ............................................................... ........... 29 7 serial interfaces ............................................ ............................................................... ................................. 32 7.1 usb interface .............................................. ............................................................... ......................... 32 7.2 uart interface ............................................ ............................................................... ........................ 32 7.2.1 uart configuration while reset is active ................. ........................................................... 33 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 6 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
7.3 programming and debug interface ............................ ............................................................... ........... 34 7.3.1 instruction cycle ........................................ ............................................................... .............. 34 7.3.2 multi-slave operation .................................... ............................................................... .......... 34 7.3.3 spi-lock and dfu encryption .............................. ............................................................... ... 35 7.4 bit-serialiser interface ................................... ............................................................... ........................ 35 7.5 i2c interface .............................................. ............................................................... ............................ 35 8 interfaces ................................................... ............................................................... .................................... 36 8.1 programmable i/o ports, pio ................................ ............................................................... ............... 36 8.1.1 lcd segment driver ....................................... ............................................................... ........ 36 8.2 analogue i/o ports, aio .................................... ............................................................... ................... 36 8.3 capacitive touch sensor .................................... ............................................................... .................. 37 8.4 led drivers ................................................ ............................................................... .......................... 39 9 audio interface .............................................. ............................................................... ................................. 40 9.1 audio input and output ..................................... ............................................................... .................... 41 9.2 audio codec interface ...................................... ............................................................... .................... 41 9.2.1 audio codec block diagram ................................ ............................................................... ... 42 9.2.2 codec set-up ............................................. ............................................................... ............. 42 9.2.3 adc ...................................................... ............................................................... ................... 43 9.2.4 adc sample rate selection ................................ ............................................................... ... 43 9.2.5 adc audio input gain ..................................... ............................................................... ........ 43 9.2.6 adc pre-amplifier and a dc analogue gain .................. ........................................................ 43 9.2.7 adc digital gain ......................................... ............................................................... ............ 44 9.2.8 adc digital iir filter ................................... ............................................................... ............ 44 9.2.9 dac ...................................................... ............................................................... ................... 44 9.2.10 dac sample rate selection ............................... ............................................................... .... 44 9.2.11 dac digital gain ........................................ ............................................................... ............. 45 9.2.12 dac analogue gain ....................................... ............................................................... ......... 45 9.2.13 dac digital fir filter .................................. ............................................................... ............ 46 9.2.14 iec 60958 interface ..................................... ............................................................... ........... 46 9.2.15 microphone input ........................................ ............................................................... ............ 47 9.2.16 digital microphone inpu ts ............................... ............................................................... ......... 48 9.2.17 line input .............................................. ............................................................... .................. 49 9.2.18 output stage ............................................ ............................................................... ............... 50 9.2.19 mono operation .......................................... ............................................................... ............ 50 9.2.20 side tone ............................................... ............................................................... ................. 51 9.2.21 integrated di gital iir filter ........................... ............................................................... ........... 52 9.3 pcm interface .............................................. ............................................................... ......................... 53 9.3.1 pcm interface master/slave ............................... ............................................................... .... 54 9.3.2 long frame sync .......................................... ............................................................... .......... 54 9.3.3 short frame sync ......................................... ............................................................... .......... 55 9.3.4 multi-slot operation ..................................... ............................................................... ............ 55 9.3.5 gci interface ............................................ ............................................................... ............... 56 9.3.6 slots and sample formats ................................. ............................................................... ..... 56 9.3.7 additional features ...................................... ............................................................... ........... 57 9.3.8 pcm timing information ................................... ............................................................... ...... 58 9.3.9 pcm_clk and pcm_sync generation .......................... ...................................................... 61 9.3.10 pcm configuration ....................................... ............................................................... ........... 62 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 7 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
9.4 digital audio interface (i2s) .............................. ............................................................... ..................... 62 10 wlan coexistence interface .................................. ............................................................... ....................... 66 11 power control and regul ation ................................ ............................................................... ....................... 67 11.1 1.8v switch-mode regulator ................................ ............................................................... ................ 71 11.2 1.35v switch-mode r egulator ............................... ............................................................... ............... 71 11.3 1.8v and 1.35v switch-mo de regulators combined ............ .............................................................. 72 11.4 bypass ldo linear regulator ............................... ............................................................... ............... 73 11.5 low-voltage vdd_dig l inear regulator ...................... ............................................................... ........ 74 11.6 low-voltage vdd_aux l inear regulator ...................... ............................................................... ....... 74 11.7 low-voltage vdd_ana l inear regulator ...................... ............................................................... ....... 74 11.8 voltage regula tor enable .................................. ............................................................... ................... 74 11.9 external regu lators and power s equencing .................. ............................................................... ...... 75 11.10reset, rst# .............................................. ............................................................... ........................... 75 11.10.1 digital pin states on reset ............................ ............................................................... ......... 75 11.10.2 status after reset ..................................... ............................................................... .............. 76 11.11automatic reset protection ............................... ............................................................... ................... 76 12 battery charger ............................................. ............................................................... ................................ 77 12.1 battery charger hardwa re operating modes .................. ............................................................... ..... 77 12.1.1 off mode ................................................ ............................................................... ................. 78 12.1.2 trickle charge m ode ..................................... ............................................................... .......... 78 12.1.3 fast charge mode ........................................ ............................................................... .......... 78 12.1.4 standby mode ............................................ ............................................................... ............. 78 12.1.5 error mode .............................................. ............................................................... ................ 79 12.2 battery charger trimmi ng and calibration .................. ............................................................... ......... 79 12.3 vm battery charger control ................................ ............................................................... ................. 79 12.4 battery charger firmware and ps keys ...................... ............................................................... ......... 79 12.5 external mode ............................................. ............................................................... .......................... 79 13 example application schematic ............................... ............................................................... ..................... 81 14 example application using different power supply configuratio ns ............................................................ . 82 15 electrical characteristics .................................. ............................................................... ............................. 85 15.1 absolute maximum ratings .................................. ............................................................... ................ 85 15.2 recommended ope rating conditions .......................... ............................................................... ......... 86 15.3 input/output terminal characteristics ..................... ............................................................... ............. 87 15.3.1 regulators: availab le for external use .................. ............................................................... 87 15.3.2 regulators: for internal use only ....................... ............................................................... .... 89 15.3.3 regulator enable ........................................ ............................................................... ............ 90 15.3.4 battery charger ......................................... ............................................................... .............. 90 15.3.5 reset ................................................... ............................................................... .................... 92 15.3.6 usb ..................................................... ............................................................... .................... 93 15.3.7 clocks .................................................. ............................................................... ................... 93 15.3.8 stereo codec: analog ue to digital converter ............. ........................................................... 95 15.3.9 stereo codec: digital to analogue converter ............. ........................................................... 96 15.3.10 digital ................................................ ............................................................... ...................... 97 15.3.11 led driver pads ........................................ ............................................................... ............. 97 15.3.12 auxiliary adc .......................................... ............................................................... ................ 98 15.3.13 auxiliary dac .......................................... ............................................................... ................ 98 15.4 esd protection ............................................ ............................................................... ......................... 99 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 8 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
16 power consumption ........................................... ............................................................... ......................... 100 17 csr green semiconductor products and rohs compliance ........ ........................................................... 102 18 software .................................................... ............................................................... ................................... 104 18.1 on-chip software .......................................... ............................................................... ...................... 104 18.1.1 stand-alone CSR8670 bga and kalimba dsp applications .... ........................................... 104 18.1.2 bluecore hci stack ..................................... ............................................................... ........ 105 18.2 off-chip software ......................................... ............................................................... ....................... 105 18.2.1 CSR8670 develo pment kit ................................. ............................................................... .. 105 18.2.2 extension program support ............................... ............................................................... ... 106 19 ordering information ........................................ ............................................................... ............................ 107 19.1 CSR8670 development kit o rdering information .............. ............................................................... . 107 20 tape and reel information ................................... ............................................................... ....................... 108 20.1 tape orientation .......................................... ............................................................... ....................... 108 20.2 tape dimensions ........................................... ............................................................... ..................... 108 20.3 reel infor mation .......................................... ............................................................... ....................... 109 20.4 moisture sensitiv ity level ................................ ............................................................... ................... 110 21 document references ......................................... ............................................................... ........................ 111 terms and definitions ......................................... ............................................................... .................................. 112 list of figures figure 1.1 pinout diagram ...................................... ............................................................... .......................... 12 figure 2.1 simplified circuit bt_rf ............................ ............................................................... ...................... 21 figure 3.1 clock architecture .................................. ............................................................... .......................... 23 figure 3.2 tcxo clock accuracy ................................. ............................................................... .................... 25 figure 5.1 kalimba dsp interface to internal functions ......... ............................................................... .......... 28 figure 6.1 serial quad i/o flash interface ..................... ............................................................... ................... 30 figure 7.1 universal asynchronous r eceiver transmit ter (uart) .. ............................................................... . 32 figure 7.2 break signal ........................................ ............................................................... ............................. 33 figure 8.1 capacitive touch se nsor block diagram ............... ............................................................... .......... 37 figure 8.2 led equivalent circuit .............................. ............................................................... ....................... 39 figure 9.1 audio inter face ..................................... ............................................................... ............................ 40 figure 9.2 audio codec input a nd output stages ................. ............................................................... ............ 42 figure 9.3 audio input gain .................................... ............................................................... .......................... 43 figure 9.4 example circuit for spdif interface (co-axial) ...... ............................................................... .......... 46 figure 9.5 example circuit for spd if interface (optical) ....... ............................................................... ........... 47 figure 9.6 microphone biasi ng .................................. ............................................................... ........................ 48 figure 9.7 differential input .................................. ............................................................... ............................. 49 figure 9.8 single-ended i nput .................................. ............................................................... ......................... 50 figure 9.9 speaker output ...................................... ............................................................... .......................... 50 figure 9.10 side tone .......................................... ............................................................... ............................... 51 figure 9.11 pcm interface master ............................... ............................................................... ....................... 54 figure 9.12 pcm interface slave ................................ ............................................................... ........................ 54 figure 9.13 long frame sync (shown with 8-bit companded sample) ............................................................ 55 figure 9.14 short frame sync (s hown with 16-bi t sample) ........ ............................................................... ....... 55 figure 9.15 multi-slot operation with 2 slots and 8-bit compande d samples ................................................... 5 6 figure 9.16 gci interface ...................................... ............................................................... .............................. 56 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 9 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
figure 9.17 16-bit slot length an d sample formats .............. ............................................................... ............. 57 figure 9.18 pcm master timing long frame sync .................. ............................................................... .......... 59 figure 9.19 pcm master timing short frame sync ................. ............................................................... .......... 59 figure 9.20 pcm slave timing long frame sync ................... ............................................................... ........... 61 figure 9.21 pcm slave timing short frame sync .................. ............................................................... ........... 61 figure 9.22 digital audio interface modes ...................... ............................................................... .................... 63 figure 9.23 digital audio interface slave timing ............... ............................................................... ................. 64 figure 9.24 digital audio interface master timing .............. ............................................................... ................ 65 figure 11.1 1.80v and 1.35v dual-supply switch-mode system confi guration ................................................ 68 figure 11.2 1.80v parallel-supply switch-mode system configurati on ............................................................ . 69 figure 11.3 external 1.8v s ystem configuration ................. ............................................................... ............... 70 figure 11.4 1.8v switch-mode regu lator output configuration .... ............................................................... ..... 71 figure 11.5 1.35v switch-mode regulator output configuration ... ............................................................... .... 72 figure 11.6 1.8v and 1.35v switch-mode regulators outputs parall el configuration ...................................... 73 figure 12.1 battery char ger mode-to-mode tra nsition diagram .... ............................................................... .... 78 figure 12.2 battery charger external mode typical configuration ............................................................... ..... 80 figure 14.1 external 1.8v suppl y example application ........... ............................................................... ........... 82 figure 14.2 external 3.3v suppl y example application ........... ............................................................... ........... 83 figure 14.3 usb dongle example application ..................... ............................................................... ............... 84 figure 18.1 stand-alone CSR8670 bga and kalimba dsp applications ........................................................ 104 figure 18.2 bluecore hci stack ................................. ............................................................... ...................... 105 figure 20.1 tape orient ation ................................... ............................................................... ......................... 108 figure 20.2 tape dimensions .................................... ............................................................... ....................... 108 figure 20.3 reel dimens ions .................................... ............................................................... ........................ 109 list of tables table 3.1 ps key values for cdma/3g phone tcxo ................. ............................................................... .... 23 table 3.2 external clock sp ecifications ........................ ............................................................... .................... 24 table 3.3 crystal specification ................................ ............................................................... .......................... 26 table 7.1 possible uart s ettings ............................... ............................................................... ..................... 33 table 7.2 instruction cycle for a spi transaction .............. ............................................................... ............... 34 table 9.1 alternative functions of the digital audio bus interfa ce on the pcm interface ............................... 40 table 9.2 adc audio input gain rate ............................ ............................................................... .................. 44 table 9.3 dac digital gain ra te selection ...................... ............................................................... ................. 45 table 9.4 dac analogue gain rat e selection ..................... ............................................................... ............. 45 table 9.5 sidetone gain ........................................ ............................................................... ............................ 52 table 9.6 pcm master timing .................................... ............................................................... ....................... 58 table 9.7 pcm slave timing ..................................... ............................................................... ........................ 60 table 9.8 alternative functions of the digital audio bus interfa ce on the pcm interface ............................... 62 table 9.9 digital audio inte rface slave timing ................. ............................................................... ................ 64 table 9.10 i2s slave mode timing ............................... ............................................................... ....................... 64 table 9.11 digital audio in terface master timing ............... ............................................................... ................ 65 table 9.12 i2s master mode timing parameters, ws and sck as outp uts ...................................................... 65 table 11.1 recommended configurations for power control and regu lation ................................................... 67 table 11.2 pin states on reset ................................. ............................................................... .......................... 75 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 10 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
table 12.1 battery charger operating modes determined by battery voltage and current ............................. 77 table 15.1 esd handling ratings ................................ ............................................................... ....................... 99 table 17.1 chemical limits for green semiconductor products .... ............................................................... ... 102 list of equations equation 3.1 crystal calibration using pskey_ana_ftrim_offset .. ............................................................ 25 equation 3.2 example o f pskey_ana_ftrim_offse t value fo r 2402.01 68mhz .......................................... 25 equation 3.3 example o f pskey_ana_ftrim_offse t value fo r 2401.98 32mhz .......................................... 26 equation 8.1 led current ....................................... ............................................................... .............................. 39 equation 8.2 led pad volta ge ................................... ............................................................... .......................... 39 equation 9.1 iir filte r transfer function , h(z) ................ ............................................................... ...................... 53 equation 9.2 iir filter plus dc blocking transfer function, h dc (z) ........................................................... ......... 53 equation 9.3 pcm_clk frequency generated using the internal 48mh z clock ................................................ 62 equation 9.4 pcm_sync frequency relative to pcm_clk ............ ............................................................... .... 62 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 11 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
1 package information 1.1 pinout diagram g-tw-0004771.1.1 k3 m4 j3 m9 m1 0 m8 m7 m6 m5 b8 c1 c2 b3 b2 b1 a3 c3 e3 d3 c4 c5 c6 f3 e1 b5 a4 b4 a5 g3 j1 g1 f1 c8 k1 a8 a1 d1 h3 h1 a2 g2 f2 e2 l1 l2 d2 b6 b7 a6 a7 k2 l3 h2 j2 c7 a b c d e f g h j k l 1234567891011 a9 a10 a11 b9 b10 c9 c10 a12 12 m1 m b11 b12 c11 c12 m2 m3 m1 1 m1 2 orientation from top of device h12 j12 k12 g12 h11 j11 k11 g11 f12 f11 d1 2 e12 l12 l11 l4 l5 k4 k5 k8 k9 k10 k6 k7 l8 l9 l10 l6 l7 d1 1 e11 h10 j10 g10 f10 d1 0 e10 g6 g7 f6 f7 figure 1.1: pinout diagram 1.2 device terminal functions radio ball pad type supply domain description bt_rf a3 rf vdd_bt_radio bluetooth 50 transmitter output / receiver input production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 12 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
synthesiser and oscillator ball pad type supply domain description xtal_in c1 analogue vdd_aux for crystal or external clock input xtal_out b1 drive for crystal uart ball pad type supply domain description uart_tx m3 bidirectional with weak pull-up vdd_pads_1 uart data output. uart_rx m2 bidirectional with strong pull-up uart data input. uart_rts k3 bidirectional with weak pull-up uart request to send, active low. alternative function pio[16]. uart_cts l3 bidirectional with weak pull-down uart clear to send, active low. usb ball pad type supply domain description usb_p m9 bidirectional vdd_usb usb data plus with selectable internal 1.5k? pull-up resistor usb_n m10 usb data minus pcm interface ball pad type supply domain description pcm_out h3 bidirectional with weak pull-down vdd_pads_1 synchronous data output. alternative function pio[18]. pcm_in f1 bidirectional with weak pull-down synchronous data input. alternative function pio[17]. pcm_sync h2 bidirectional with weak pull-down synchronous data sync. alternative function pio[19]. pcm_clk g2 bidirectional with weak pull-down synchronous data clock. alternative function pio[20]. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 13 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
spi interface ball pad type supply domain description spi_miso l2 output with weak pull- down vdd_pads_1 spi data output spi_mosi g3 input with weak pull- down spi data input spi_cs# m1 input with strong pull-up chip select for spi, active low spi_clk e1 input with weak pull- down spi clock pio port ball pad type supply domain description pio[15] l6 bidirectional with weak pull-down vdd_pads_2 programmable input / output line pio[14] m7 pio[13] j10 pio[12] k10 pio[11] l9 pio[10] m8 pio[9]/nc l10 bidirectional with weak pull-down vdd_pads_2 if interrupts are enabled on vchg the logic signal is internal ly routed to pio[9] to enable CSR8670 bga to wake up from deep sleep when vchg is pressed, see section 8.1. pio[8]/nc l8 bidirectional with weak pull-down vdd_pads_2 if interrupts are enabled on vregenable the logic signal is internally routed to pio[8] to enable CSR8670 bga to wake up from deep sleep when vregenable is pressed, see section 8.1. pio[7] k9 bidirectional with weak pull-down vdd_pads_2 programmable input / output line pio[6] m6 pio[5] l7 pio[4] k8 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 14 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
pio port ball pad type supply domain description pio[3] k6 bidirectional with weak pull-down vdd_pads_1 programmable input / output line pio[2] m5 pio[1] l5 pio[0] l4 aio[1] d1 bidirectional vdd_aux analogue programmable input / output line aio[0] c4 serial quad i/o flash ball pad type supply domain description qspi_sram_cs# b10 bidirectional with strong pull-up vdd_pads_3 spi ram chip select. alternative function pio[24]. qspi_sram_clk b12 bidirectional with strong pull-down vdd_pads_3 spi ram clock. alternative function pio[22]. qspi_flash_cs# d11 bidirectional with strong pull-up vdd_pads_3 spi flash chip select. alternative function pio[23] qspi_flash_clk c12 bidirectional with strong pull-down vdd_pads_3 spi flash clock. alternative function pio[21]. qspi_flash_io[3] d12 bidirectional with strong pull-down vdd_pads_3 serial quad i/o flash data bit 3. alternative function pio[28]. qspi_flash_io[2] c10 bidirectional with strong pull-down vdd_pads_3 serial quad i/o flash data bit 2. alternative function pio[27]. qspi_flash_io[1] b11 bidirectional with strong pull-down vdd_pads_3 serial quad i/o flash data bit 1. alternative function pio[26]. qspi_flash_io[0] c11 bidirectional with strong pull-down vdd_pads_3 serial quad i/o flash data bit 0. alternative function pio[25]. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 15 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
capacitive touch sensor ball pad type supply domain description cap_sense[5] f2 analogue input vdd_aux_1v8 capacitive touch sensor input cap_sense[4] f3 cap_sense[3] e3 cap_sense[2] e2 cap_sense[1] d3 cap_sense[0] d2 test and debug ball pad type supply domain description rst# l1 input with strong pull-up vdd_pads_1 reset if low. input debounced so must be low for >5ms to cause a reset. codec ball pad type supply domain description mic_lp a10 analogue in vdd_audio microphone input positive, left mic_ln a11 microphone input negative, left mic_rp c7 analogue in vdd_audio microphone input positive, right mic_rn c8 microphone input negative, right mic_bias_a a9 analogue out vbat / vout_3v3 microphone bias a mic_bias_b b8 analogue out vbat / vout_3v3 microphone bias b spkr_lp c5 analogue out vdd_audio_drv speaker output positive, left spkr_ln c6 speaker output negative, left spkr_rp b7 analogue out vdd_audio_drv speaker output positive, right spkr_rn a7 speaker output negative, right au_ref b9 analogue in vdd_audio decoupling of audio reference (for high- quality audio) production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 16 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
led drivers ball pad type supply domain description led[2] m4 open drain vdd_pads_1 open drain tolerant to 4.25v led driver. alternative function po[31]. led[1] k5 led driver. alternative function po[30]. led[0] k4 led driver. alternative function po[29]. power supplies and control ball description chg_ext f11 external battery charger control lx_1v35 l12 1.35v switch-mode power regulator output lx_1v8 j12 1.8v switch-mode power regulator output smp_vbat k12 1.8v and 1.35v switch-mode power supply regulator inputs. must be at the same potential as vbat. smps_1v35_sense m11 1.35v switch-mode power regulator sense input smps_1v8_sense f10 1.8v switch-mode power regulator sense input smps_3v3 k11 alternative supply via bypass regulator for 1.8v and 1.35v swit ch- mode power supply regulator inputs. must be at the same potential as vout_3v3. vbat h12 battery positive terminal vbat_sense h11 battery charger sense input vchg g11, g12 battery charger input vout_3v3 f12 3.3v bypass linear regulator output vdd_ana c2 analogue ldo linear regulator output (1.35v) vdd_audio a8 positive supply for audio (1.35v) vdd_audio_drv a6 positive supply for audio driver (1.8v) vdd_aux c3 auxiliary ldo linear optional regulator output (1.35v) / auxili ary circuit input vdd_aux_1v8 a1 auxiliary and analogue ldo linear regulator input (1.8v) / auxi liary circuits vdd_bt_lo a2 bluetooth radio local oscillator supply (1.35v) production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 17 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
power supplies and control ball description vdd_bt_radio a5 bluetooth radio supply, also opt ional sense input for 1.35v analogue linear regulator vdd_dig_eflash e12 digital ldo linear regulator output (0.85 to 1.2v) vdd_eflash_1v8 j1 flash supply input vdd_pads_1 k1 1.7v to 3.6v positive supply input for input/output ports: rst# uart pcm spi pio[3:0] vdd_pads_2 k7 1.7v to 3.6v positive supply input for digital input/output por ts pio[15:4] vdd_pads_3 a12 1.7v to 3.6v positive supply i nput for serial quad i/o flash po rt vdd_usb l11 positive supply for usb ports vregenable e10 regulator enable input vregin_dig e11 digital ldo linear regulator input vss_audio c9 ground connection for audio vss_audio_drv b6 ground connection for audio driver vss_bt_lo_aux b2 ground connections for analogue ci rcuitry and bluetooth radio l ocal oscillator vss_bt_rf a4, b5 bluetooth radio ground vss_dig d10, f7, g7, g10, h10 ground connection for internal d igital circuitry and pads vss_smps_1v35 m12 1.35v switch-mode regulator ground vss_smps_1v8 j11 1.8v switch-mode regulator ground unconnected terminals ball description nc b3, b4, f6, g1, g6, h1, j2, j3, k2 leave unconnected production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 18 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
1.3 package dimensions g-tw-0004769.4.3 c a 2x a1 corner index area c c 3 f g c seating plane 2 ?h ?j ?b nx 1 m m c c ab c a a 2x d c a (a3) (a2) a1 e e1 se e sd e bottom view d1 to p vi e w 12 11 10 9 8 7 6 5 4 3 2 1 l k j h g f e d c b a m dimension min typ max dimension min typ max a 0.8 0.87 1.0 e - 0.5 - a1 0.16 - 0.26 f - 0.10 - a2 - 0.21 - g - 0.08 - a3 - 0.45 - h - 0.15 - a - 0.05 - j - 0.08 - b 0.27 - 0.37 n - 112 - d 6.45 6.5 6.55 sd - 0.25 - d1 - 5.5 - se - 0.25 - e 6.45 6.5 6.55 ball diameter - 0.3 - e1 - 5.5 - solder land opening - 0.275 - notes 1. dimension b is measured at the ma ximum solder ball diameter, pa rallel to datum plane c. 2. datum c (seating plane) is defined by the spherical crowns of t he solder ball. 3. parallelism measurement shall excl ude any effect of mark on top surface of package. description 112-ball very thin, fine pitch ball grid array (vfbga) package size 6.5 x 6.5 x 1mm jedec mo-225 pitch 0.5 units mm production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2011 page 19 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
1.4 pcb design and assembly considerations this section lists recommendations to achieve maximum board-lev el reliability of the 6.5 x 6.5 x 1mm vfbga 112?ball package: nsmd lands, i.e. lands smaller than the solder mask aperture, a re preferred because of the greater accuracy of the metal definition process compared to the solder mask process. with solder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which can cause stress concentration and act as a point for crack ini tiation. ideally, use via-in-pad technology to achieve truly nsmd lands. where this is not possible, a maximum of one trace connected to each land is preferred and this trace sh ould be as thin as possible, this needs to take into consideration its current carrying and the rf require ments. 35m thick (1oz) copper lands are recommended rather than 17m thick (0.5oz). this results in a greater standoff which has been proven to provide greater reliability d uring thermal cycling. land diameter should be the same as that on the package to achi eve optimum reliability. solder paste is preferred to flux during the assembly process b ecause this adds to the final volume of solder in the joint, increasing its reliability. when using a nickel gold plating finish, the gold thickness sho uld be kept below 0.5m to prevent brittle gold/tin intermetallics forming in the solder. 1.5 typical solder reflow profile see typical solder reflow profile for lead-free devices for information. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 20 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
2 bluetooth modem 2.1 rf ports 2.1.1 bt_rf CSR8670 bga contains an on-chip balun which combines the balanc ed outputs of the pa on transmit and produces the balanced input signals for the lna required on receive. no matching components are needed as the receive mode impedance is 50 and the transmitter has been optimised to deliver power in a 50 load. g-tw-0005523.2.2 + _ pa + _ lna bt_rf on-chip balun vdd vss_bt_rf figure 2.1: simplified circuit bt_rf 2.2 rf receiver the receiver features a near-zero if architecture that enables the channel filters to be integrated onto the die. sufficient out-of-band blocking specification at the lna input enables the receiver to operate in close proximity to gsm and w?cdma cellular phone transmitters without being desens itised. a digital fsk discriminator means that no discriminator tank is needed and its excellent performance i n the presence of noise enables CSR8670 bga to exceed the bluetooth requirements for co?channel and adjacent c hannel rejection. for edr, the demodulator contains an adc which digitises the if received signal. this information is then passed to the edr modem. 2.2.1 low noise amplifier the lna operates in differential mode and takes its input from the balanced port of the on-chip balun. 2.2.2 rssi analogue to digital converter the adc implements fast agc. the adc samples the rssi voltage o n a slot-by-slot basis. the front-end lna gain is changed according to the measured rssi value, keeping the fi rst mixer input signal within a limited range. this improves the dynamic range of t he receiver, improving performan ce in interference-limited environments. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 21 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
2.3 rf transmitter 2.3.1 iq modulator the transmitter features a direc t iq modulator to minimise freq uency drift during a transmit timeslot, which results in a controlled modulation index. digital baseband transmit cir cuitry provides the required spectral shaping. 2.3.2 power amplifier the internal pa output power is software controlled and configu red through a ps key. the internal pa on the CSR8670 bga has a maximum output power that enables it to opera te as a class 1, class 2 and class 3 bluetooth radio without requiring an external rf pa. 2.4 bluetooth radio synthesiser the bluetooth radio synthesiser is fully integrated onto the di e with no requirement for an external vco screening can, varactor tuning diodes, lc resonators or loop filter. the synthesiser is guaranteed to lock in sufficient time across the guaranteed temperature range to meet the bluetooth v 3.0 specification. 2.5 baseband 2.5.1 burst mode controller during transmission the bmc constructs a packet from header inf ormation previously loaded into memory-mapped registers by the software and payload data/voice taken from the appropriate ring buffer in the ram. during reception, the bmc stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer in ram. this architecture minimises the intervention required b y the processor during transmission and reception. 2.5.2 physical layer hardware engine dedicated logic performs the following: forward error correction header error control cyclic redundancy check encryption data whitening access code correlation audio transcoding firmware performs the following voice data translations and ope rations: a-law/-law/linear voice data (from optional host) a-law/-law/cvsd (over the air) voice interpolation for lost packets rate mismatch correction the hardware can be used as part of a fully compliant bluetooth v3.0 specification system. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 22 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
3clock generation CSR8670 bga requires a bluetooth reference clock frequency of 1 9.2mhz to 42mhz from either an externally connected crystal or from an external tcxo source. all CSR8670 bga internal digital clocks are generated using a p hase locked loop, which is locked to the frequency of either the external 19.2mhz to 42mhz reference clock source or safely free-runs at a reduced frequency. the bluetooth operation determines the use of the watchdog cloc k in low-power modes. 3.1 clock architecture g-tw-0000189.3.3 bluetooth radio auxiliary pll digital circuitry reference clock figure 3.1: clo ck architecture 3.2 input frequencies and ps key settings configure the CSR8670 bga to operate with the chosen reference frequency. set pskey_ana_freq for all frequencies with an integer multiple of 250khz. the input frequ ency default setting in CSR8670 bga is 26mhz depending on the software build. full details are in the softwa re release note for the specific build from www.csrsupport.com . the following cdma/3g phone tcxo frequencies are supported: 19. 2, 19.44, 19.68, 19.8 and 38.4mhz. the value of the ps key is a multiple of 1k hz, so 38.4mhz i s selected by using a ps key value of 38400. reference crystal frequency (mhz) pskey_ana_freq (khz) 19.20 19200 19.44 19440 19.68 19680 19.80 19800 38.40 38400 n x 0.25 n x 250 26.00 (default) 26000 table 3.1: ps key values for cdma/3g phone tcxo production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 23 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
3.3 external reference clock 3.3.1 input: xtal_in apply the external reference clock to the CSR8670 bga xtal_in i nput. CSR8670 bga is configured to accept the external reference clock at xtal_in by connecting xtal_out to g round. supply the external clock with either a digital level square wa ve or low-level sinu soidal, coupling this directly to the xtal_in without the need for additional components. the dc cloc k level is permitted at any voltage level between the supply rails, i.e. vss_bt_lo_aux to vdd_aux. the external reference clock is required in active and deep sle ep modes, so must be present when CSR8670 bga is enabled. table 3.2 lists the specification for the external reference cl ock signal. min typ max unit frequency (a) 19.2 26 42 mhz duty cycle 40:60 50:50 60:40 - edge jitter (at zero crossing) - - 10 ps rms signal level ac coupled sinusoid 0.2 0.4 vdd_aux (b) v pk-pk dc coupled digital v il - vss_bt_lo_aux - v v ih - vdd_aux (b) - v table 3.2: external clock specifications (a) the frequency should be an int eger multiple of 250khz except fo r the cdma/3g frequencies (b) vdd_aux is 1.35v nominal 3.3.2 xtal_in impedance in external mode the impedance of xtal_in does not change significantly between operating modes. when transitioning from deep sleep to an active state a spike of up to 1pc is possible. for this reason csr recommends using a buffered clock input. 3.3.3 clock timing accuracy as figure 3.2 shows, the 250ppm timing accuracy on the external clock is required 2ms after the firmware begins to run. this guarantees that the firmware maintains timing accu racy in accordance wit h the bluetooth v3.0 specification. radio activity occurs after 6ms after the firmwa re starts. therefore, at this point the timing accuracy of the external clock source must be within 20ppm. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 24 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0000190.3.2 clock accuracy 0 20ppm 6 250ppm 2 1000ppm ms after firmware clk_req firmware activity pskey_clock_startup_delay firmware activity radio activity figure 3.2: tcxo clock accuracy 3.4 crystal oscillator : xtal_in and xtal_out CSR8670 bga contains a crystal dri ver circuit that acts as a tr ansconductance amplifier driving an external crystal between xtal_in and xtal_out. t he crystal driver circuit forms a pierce oscillator with the external crystal. 3.4.1 crystal calibration the actual crystal frequency depends on the capacitance of xtal _in and xtal_out o n the pcb and the CSR8670 bga, as well as the capacitance of the crystal. correct calibration of the bluetooth radio is done on a per- device basis on the production line, with the trim value stored in non-volatile memory (ps key). crystal calibration uses a single measurement. the measurement finds the actual offset from the desired frequency and the offset is st ored in pskey_ana_ftrim_ offset. the firmwar e then compensates for the frequency offset o n th e csr 86 7 0 bga . typ i cal ly , a tx star t rad i o te st i s p er fo rme d to obtain the actual frequency and it is compared against the output frequency with the requested frequency using an rf analyser. the tes t station calculates the offset ratio and programs it into pskey_ana_ftrim_offset. the v alue in pskey_ana_ft rim_offset is a 16-bit 2's complement signed integer which specifies the fracti onal part of the ratio between the true crystal frequency, f actual , and the value set in pskey_ana_freq, f nominal . equation 3.1 shows the value of pskey_ana_ftrim_off set in parts per 2 20 rounded to the nearest integer. for more information on txstart radio test see bluetest user guide . pskey_ana_ftrim_offset = ( f actual f nominal ?1)2 20 equation 3.1: crystal calibration using pskey_ana_ftrim_offset for a requested frequency of 2402mhz with an actual output of 2 402.0168mhz the pskey_ana_ftrim_offset value is 7, see equation 3.2. pskey_ana_ftrim_offset = ( 2402.0168 2402 ?1)2 20 7 equation 3.2: example of pskey_an a_ftrim_offset va lue for 2402. 0168mhz for a requested frequency of 2402mhz with an actual output of 2 401.9832mhz the pske y_ana_ftrim_offset value is -7 (0xfff9), see equation 3.3. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 25 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
pskey_ana_ftrim_offset = ( 2401.9832 2402 ?1)2 20 ?7 equation 3.3: example of pskey_an a_ftrim_offset va lue for 2401. 9832mhz 3.4.2 crystal specification table 3.3 shows the specification for an external crystal. parameter min typ max unit frequency 19.2 26 42 mhz frequency tolerance - - 10 ppm frequency stability - - 20 ppm table 3.3: crystal specification production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 26 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
4 bluetooth stack microcontroller the CSR8670 bga uses a 16-bit risc 80mhz mcu for low power cons umption and efficient use of memory. it contains a single-cycle multiplier and a mem ory protec tion unit for the vm accelerator, see section 4.1. the mcu, interrupt controller and event timer run the bluetooth software stack and control the bluetooth radio and host interfaces. 4.1 vm accelerator CSR8670 bga contains a vm accelerator alongside the mcu. this h ardware accelerator improves the performance of vm applications. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 27 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
5 kalimba dsp the kalimba dsp is an open platform dsp enabling signal process ing functions to be performed on over-air data or codec data to enhance audio applications. figure 5.1 shows t he kalimba dsp interfaces to other functional blocks within CSR8670 bga. g-tw-0005522.2.2 memory management unit mcu register interface (including debug) dsp mmu port pio in/out irq to subsystem irq from subsystem 1 s timer clock programmable clock = 80mhz data memory inteface address generators instruction decode program flow clock select internal control register mmu interface interrupt controller timer mcu window flash window debug alu pio dsp program control registers dsp rams dm2 dm1 pm kalimba dsp core dsp, mcu and memory window control dsp data memory 2 interface (dm2) dsp data memory 1 interface (dm1) dsp program memory interface (pm) figure 5.1: kalimba dsp interface to internal functions the key features of the dsp include: 80mips performance, 24-bit fixed point dsp core 2 single?cycle macs ; 24 x 24-bit mu ltiply and 56-bit accumulate 32-bit instruction word separate program memory and dual data memory, allowing an alu o peration and up to 2 memory accesses in a single cycle zero overhead looping, including a very low-power 32-instructio n cache zero overhead circular buffer indexing single cycle barre l shifter with up to 56-bit in put and 56-bit output multiple cycle divide (pe rformed in t he background) bit reversed addressing orthogonal instruction set low overhead interrupt for more information see kalimba architecture 3 dsp user guide . production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 28 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
6 memory interface and management 6.1 memory management unit the mmu provides dynamically allocated ring buffers that hold t he data that is in transit between the host, the air or the kalimba dsp. the dynamic allocation of memory ensures effic ient use of the available ram and is performed by a hardware mmu to minimise the overheads on the processor du ring data/voice transfers. the use of dma ports also helps with efficient transfer of data to other peripherals . 6.2 system ram 56kb of integrated ram supports the risc mcu and is shared betw een the ring buffers for holding voice/data for each active connection and the general-purpose memory required by the bluetooth stack. 6.3 kalimba dsp ram additional integrated ram provides support for the kalimba dsp: 32k x 24-bit for data memory 1 (dm1) 32k x 24-bit for data memory 2 (dm2) 12k x 32-bit for program memory (pm) note: the kalimba dsp can also execute directly from internal flash o r external sqif, using a 1k-instruction on-chip cache. 6.4 eflash memory (16mb) the internal flash memory provides 16mb of internal code and da ta storage. the internal flash stores CSR8670 bga settings and program code, and kalimba dsp coprocessor code and data. for improved performance, the internal flash memory has 45ns access time and is organised as 64-bit wi de. 6.5 serial quad i/o flash interface (sqif) CSR8670 bga supports external serial flash and sram ics. this e nables additional data storage areas for device- specific data. CSR8670 bga supports serial single, dual or quad i/o devices with a 1-bit, 2-bit or 4-bit multiplexed i/o flash-memory interface. figure 6.1 shows a typical connecti on between the CSR8670 bga and a serial flash and sram ic. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 29 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0005514.4.2 memory management unit serial quad i/o flash spi sram mcu program mcu data kalimba dsp data kalimba dsp program mcu kalimba dsp qspi_flash_clk qspi_sram_cs# qspi_sram_clk qspi_flash_cs# qspi_io[0] qspi_io[1] qspi_io[2] qspi_io[3] sqif clk cs# di/io0 do/io1 wp#/io2 reset#/hold#/io3 clk cs# hold# si so figure 6.1: serial quad i/o flash interface the sqif interface on the CSR8670 bga supports: flash and sram serial memory, which are also visible in the mcu and kalimba dsp program address space mcu and kalimba dsp data access through a generic window concurrent program and / or data accesses from the mcu and / or kalimba dsp (although efficiency suffers) separate prefetc h buffers for mcu program, mcu data, kalimba ds p program, kalimba dsp data: each buffer is 4 x 16-bit defined minimum length prefetch prefetch continues if accesses are contiguous (and buffer not f ull) prefetch does not automatically restart as buffer empties prefetch is enabled and disabled by software control, which ena bles optimisation of sequential / random data access patterns flash and sram use same prefetch buffer winbond, sst and macronix (and compatible) selected serial flas h devices up to 64mb with 1-bit, 2-bit and 4-bit wide transfers microchip and onsemi (and compatible) selected serial sram devi ces up to 512kb with 1-bit wide transfers flash / sram performance: clocks up to 80/16mhz the control and address overhead is 14/24 cycles per burst read , with support for word read quad continuous (winbond) and high speed read quad (sst). sst indexe d instructions are not supported. data transfer is 4/1 6 cycles per 16-bits flash instruction sequences: requires considerable (run-time) programmable configuration set up for either read, or write (not both) software configures sqif for specific flash attached sram instruction sequences: production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 30 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga free datasheet http://www.datasheetlist.com/
interface is hard wired reads and writes can interleave without need for any reconfigur ation all other management of serial flash / sram via software: memory mapped registers support transfers of data to and from t he flash software needs to read the serial flash jedec id in order to in dex a table of flash characteristics software driven sequence to enable, e.g. the winbond continuous read mode note: CSR8670 bga cannot boot up from serial flash. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 31 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
7 serial interfaces 7.1 usb interface CSR8670 bga has a full-speed (12mbps) usb interface for communi cating with other compatible digital devices. the usb interface on CSR8670 bga acts as a usb peripheral, resp onding to requests from a master host controller. CSR8670 bga supports the universal serial bus s pecification, revision v2.0 (usb v2.0 spe cification) and usb battery charging specification , available from http://www.usb.org . for more information on how to integrate the usb interface on CSR8670 bga see the bluetooth and usb design considerations application note . as well as describing usb basics and architecture, the applicat ion note describes: power distribution for high and low bus-powered configurations power distribution for self-powered configuration, which includ es usb vbus monitoring usb enumeration electrical design guidelines for the power supply and data line s, as well as pcb tra cks and the effects of ferrite beads usb suspend modes and bluetooth low-power modes: global suspend selective suspend, includes remote wake wake on bluetooth, includes permitted devices and set-up prior to selective suspend suspend mode current draw pio status in suspend mode resume, detach and wake pios battery charging from usb, which describes dead battery provisi on, charge currents, charging in suspend modes and usb vbus voltage consideration usb termination when interface is not in use internal modules, certification and non-specification compliant operation 7.2 uart interface this is a standard uart interface for communicating with other serial devices. CSR8670 bga uart interface provides a simple mechanism for comm unicating with other serial devices using the rs-232 protocol. g-tw-0000198.3.2 uart_tx uart_rx uart_rts uart_cts figure 7.1: universal asynchronous receiver transmitter (uart) figure 7.1 shows the 4 signals that implement the uart function . when CSR8670 bga is connected to another digital device, uart_rx and uart_tx transfer data between the 2 devices. the remaining 2 signals, uart_cts and uart_rts, implement rs232 hardware flow control where both are active low indicators. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 32 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
if uart_cts and uart_rts are not required for hardware flow con trol, they are reconfigurable as pio. uart configuration parameters, such as baud rate and packet for mat, are set using CSR8670 bga firmware. note: to communicate with the uart at its maximum data rate using a s tandard pc, an accelerated serial port adapter card is required for the pc. table 7.1 shows the possible uart settings. parameter possible values baud rate minimum 1200 baud (2%error) 9600 baud (1%error) maximum 4mbaud (1%error) flow control rts/cts or none parity none, odd or even number of stop bits 1 or 2 bits per byte 8 table 7.1: possible uart settings the uart interface resets CSR8670 bga on reception of a break s ignal. a break is identified by a continuous logic low (0v) on the uart_rx terminal, as figure 7.2 shows. if t brk is longer than the value defined by the pskey_hostio_uart_reset_timeout, a reset occurs. this feature e nables a host to ini tialise the system to a known state. also, CSR8670 bga can issue a break character fo r waking the host. g-tw-0000250.5.2 uart_tx t brk figure 7.2: break signal refer to pskey_uart_bitrate for m ore information about the baud rates and their values. generated baud rate is independent of selected incoming clock f requency. the uart interface is tristate while CSR8670 bga is being held in reset. this enables the user to connect other devices onto the physical uart bus. the restriction with this m ethod is that any devices connected to this bus must tristate when CSR8670 bga reset is de-asserted and the firmware begins to run. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 33 of 116 cs-127997-dsp2 www.csr.com free datasheet http://www.datasheetlist.com/
7.3 programming an d debug interface important note: the spi is for programming, configuring (ps keys) and debugging the CSR8670 bga. it is required in production. ensure the 4 spi signals are brought out to either test points or a header. csr provides development and production tools to communicate ov er the spi from a pc, although a level translator circuit is often required. all are available from cs r. CSR8670 bga uses a 16-bit data and 16-bit address programming a nd debug interface. tr ansactions occur when the internal processor is running or is stopped. data is written or read one word at a time, or the auto-increme nt feature is available for block access. 7.3.1 instruction cycle the CSR8670 bga is the slave and receives commands on spi_mosi and outputs data on spi_miso. table 7.2 shows the instru ction cycle for a spi transaction. 1 reset the spi interface hold spi_cs# high fo r two spi_clk cycles 2 write the command word take spi_cs# low and clock in the 8-bit command 3 write the address clock in the 16-bit address word 4 write or read data words clock in or out 16-bit data word(s) 5 termination take spi_cs# high table 7.2: instruction cycle for a spi transaction with the exception of reset, spi_cs# must be held low during th e transaction. data on sp i_mosi is clocked into the CSR8670 bga on the rising edge of the clock line spi_clk. w hen reading, CSR8670 bga replies to the master on spi_miso with the data changing on the falling edge of the s pi_clk. the master provide s the clock on spi_clk. taking spi_cs# high terminates the transaction. sending a command word and the address of a register for every time it is to be read or written is a significant overhead, especially when transferring large amounts of data. t o overcome this CSR8670 bga offers increased data transfer efficiency via an auto increment operation. to in voke auto increment, spi_cs# is kept low, which auto increments the addres s, while provi ding an extra 16 clock cycle s for each extra word to be written or read. 7.3.2 multi-slave operation avoid connecting CSR8670 bga in a multi-slave arrangement by si mple parallel connection of slave miso lines. when CSR8670 bga is de selected (spi_cs# = 1), the spi_miso line does not float. instead, CSR8670 bga outputs 0 if the processor is running or 1 if it is stopped. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 34 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
7.3.3 spi-lock and dfu encryption CSR8670 bga contains a couple of security features: spi-lock prevents unauthorised access to the CSR8670 bga and it s firmware. warranty: while csr has exercised all reasonable care and diligence in th e design of the spi-lock feature, csr does not warrant that the performance of the spi-lock functiona lity is fit for its intended purpose. accordingly, csr disclaims any liability arising out of the spi -lock feature to the maximum extent permitted by law. dfu encryption enables a customer to securely store, upload and transfer CSR8670 bga firmware. note: dfu encryption is unavailable at present. future revisions of f irmware will support this feature. 7.4 bit-serialiser interface CSR8670 bga includes a configurable hardware bit-serialiser blo ck. the bit-serialiser block uses up to 4 pios to form a serial interface. the bit-serialiser block is configurab le to support several interfaces, including i2c and spi. note: CSR8670 bga requires suitable firmware to support the hardware bit-serialiser interface. 7.5 i2c interface section 7.4 describes the hardware bit-serialiser interface. if it is not used, then pio[7:6] are available to form a software-drive n master i2c interface. note: as this i2c interface is software-driven it is suited to relati vely slow functions such a s driving a dot matrix lcd, keyboard scanner or eeprom. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 35 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
8interfaces 8.1 programmable i/o ports, pio 29 lines of programmable bidirectional i/o are available on the CSR8670 bga. some of the pios on the CSR8670 bga have alternative functions: 3 digital microphone interfaces for control of up to 6 digital microphones: clock on any even pios as determined by the software data on any odd pios as determined by the software bit serialiser on any pios as determined by the software lcd[15:0] directly map to pio[15:0] as determined by the softwa re. lcd[15:0] are also reflected up on to pio[31:16] note: if wake up of CSR8670 bga is required via the vchg pin, then th e operation of pio[9] is nc and should be left unconnected. otherwise, configuration of pio[9] as a pio is by setting pskey_vchg_reroute_internally_via_pio to 0xffff , for more information contact csr. if wake up of CSR8670 bga is required via the vregenable pin, t hen the operation of pio[8] is nc and should be left unconnected. otherwise, configuration of pio[8] as a pio is by setting pskey_vreg_en_reroute_internally_via_pio to 0xffff , for more information contact csr. led[2:0] directly map to po[31:29] pcm interface on pio[20:17] uart rts on pio[16] serial quad i/o flash interface on pio[28:24] note: see the relevant software release note for the implementation o f these pio lines, as they are firmware build- specific. 8.1.1 lcd segment driver it is possible to drive and cont rol small icon?based lcd segmen ts directly from the 1.7v to 3.6v pios (using the internal regulators) on the CSR8670 bga. this enables an applic ation to have a simple intuitive interface that indicates status parameters, e.g. battery level etc. the lcd is driven at a refresh rate between 50hz and 60hz (depe nding on the crystal frequency) with square wave signals applied to the common pin and the segment pin either in phase to turn off a segment or in anti-phase to charge a segment. any pio is available as the common pin and an y number of the remaining pios as segment pins. 8.2 analogue i/o ports, aio CSR8670 bga has 2 general-purpose analogue interface pins, aio[ 1:0], for accessing internal circuitry and control signals. auxiliary functions avai lable on the analogue interfac e include a 10-bit adc and a 10-bit dac. signals selectable on this interface include the band gap reference vol tage. when configured for analogue signals the voltage range is constrained by the analogue supply voltage. when confi gured to drive out digital level signals generated from within the analogue part of the device, the output voltage level is determ ined by vdd_aux. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 36 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
8.3 capacitive touch sensor CSR8670 bga capacitive touch sensor interface features: support for up to 6 capacitive touch sensing electrodes: printed on the pcb made from flex pcb configuration for individual buttons configuration for a wipe-type arrangement where 2 or more pads sense taps at each end or a wipe from one side to the other operates in deep sleep and is a programmable source for wake-up figure 8.1 shows the system block diagram for the capacitive to uch sensor interface. the interface depends on the capacitive touch sensor type. therefore the overall control of the capacitive touch senso r interface resides in the vm, so it is easily modified i n each end-user application. g-tw-0005533.3.2 mux cap_ sense[0] cap_sense[1] cap_sense[2] cap_sense[3] cap_sense[4] cap_sense[5] capacitive range control sampling front-end firmware digital processing vm adc figure 8.1: capacitive touch sensor block diagram the overall system-level specification for the capacitive touch sensor interface on the CSR8670 bga is: 6 inputs multiplexed in to 1 touch sensor on the front-end capacitances of 0pf to 50pf measured with a resolution of 4ff, where a touch is assumed to be between 50ff and 1pf each reading takes 172s: 6 pads read every 1.03ms system auto-calibrates to remove parasitic and environmental ef fects including: pcb construction temperature humidity works in normal and deep sleep modes system current is approximately 50a from the battery the touch sensor also functions like a pio production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 37 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
the system block diagram in figure 8.1 highlights the top-level architecture for the capacitive touch sensor interface, it consists of: capacitive range control: sets the rough capacitance of the touch sensor pad, which is pr oduct dependent splits into 4 integrated capacitors the vm selects which capacitors are enabled, i.e. the range cap acitance sampling front end: an internal capacitance is trimmed by the digital state machine ensuring: touch capacitance = range capacitance + internal capacitance when the internal capacitance is correctly trimmed: the sense voltage is 0v a touch changes the touch capacitance, which then changes the s ense voltage adc: uses a successive approximation, charge redistribution adc clocked at 64khz 9-bit resolution, where lsb is 2ff and full range is 1pf the internal capacitance is a 7-bit variable capacitor with 114 ff steps and 14.5pf range the internal capacitance is trimmed, putting it in the mid rang e of the adc. this enables measurements from 0pf to 50pf, where a capacitive touch is between 50ff and 1pf. digital signal conditioning: only the enabled inputs are scanned enabling fewer inputs increases readings per second averaging of adc readings reduces noise, this is software progr ammable from 1 to 64 readings in intervals to the power of 2 the internal capacitance updates using a rolling average of the adc readings, software programmable from 1 to 2 15 readings in intervals to the power of 2. for example, 32768 re adings take approximately: 5.6s if polling one pad (no averaging) 33.8s if polling 6 pads (no averaging) pulse skipping mode is possible, reducing the current consumpti on. here the system waits a programmable number of 64kh z clock cycles (maximum 2 9 ) before the next read, i.e. an 8ms maximum pause. adc trigger level is software programmable. if the threshold is crossed the firmware gets an interrupt. 6 hardware event registers store the pad number and trigger tim e, which enables t he system to sense swipes. programmable hysteresis, with one value for all pads software signal conditioning (firmware): the firmware reads adc and c int values after an interrupt as the hardware only stores the pad number and trigger time digital state machine scans pads and calibrates the internal ca pacitance if a swipe happens in deep sleep the firmware reads the trigger order and event time when it wakes up. it then reads the last adc reading for each input, not the reading that triggered the interrupt. vm: configures the hardware and gets an interrupt when a programmab le threshold is crossed selects the range capacitance decides whether an event is a valid touch for more information on CSR8670 bga capacitive touch sensor con figuration see configuring the touch sensor on CSR8670 . production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 38 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
8.4 led drivers CSR8670 bga includes a 3-pad synchronised pwm led driver for dr iving rgb leds for producing a wide range of colours. all leds are controlled by firmware. the terminals are open-drain outputs, so the led must be connec ted from a positive supply rail to the pad in series with a current-lim iting resistor. g-tw-0005534.2.2 led forward voltage, v f pad voltage, v pad ; r on = 20 r led led[2, 1 or 0] resistor voltage drop, v r led supply i led figure 8.2: led equivalent circuit from figure 8.2 it is possible to derive equation 8.1 to calcul ate i led . if a known value of current is required through the led to give a specific luminous intensity, then the value o f r led is calculated. i led = vdd ? v f r led +r on equation 8.1: led current for the led pads to act as resistance, the external series resi stor, r led , needs to be such that the voltage drop across it, v r , keeps v pad below 0.5v. equation 8.2 also applies. vdd = v f +v r +v pad equation 8.2: led pad voltage note: the led current adds to the overall current. conservative led s election extends battery life. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 39 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
9audio interface the audio interface circuit consists of: stereo/dual-mono audio codec dual analogue audio inputs dual analogue audio outputs 6 digital mems microphone inputs a configurable pcm, i2s or spdif interface for more information on CSR8670 bga audio path configuration se e the CSR8670 audio development kit (dk?8670?10060?1a). figure 9.1 shows the functional blocks of the interface. the co dec supports stereo/dual-mono playback and recording of audio signals at multiple sample rates with a 16-bit resolut ion. the adc and the dac of the codec each contain 2 independent high-quality channels. any adc or dac channel run s at its own independent sample rate. g-tw-0005507.3.2 stereo / dual-mono codec memory management unit mmu voice port register interface voice port registers pcm digital audio stereo audio codec driver pcm interface 2 x differential dac outputs 2 x differential adc inputs digital mics 6 x digital mics figure 9.1: audio interface the interface for the digital audio bus shares the same pins as the pcm codec interface described in section 9.3 which means each of the audio buses are mutually exclusive in t heir usage. table 9.1 lists these alternative functions. pcm interface spdif interface i2s interface pcm_out spdif_out sd_out pcm_in spdif_in sd_in pcm_sync - ws pcm_clk - sck table 9.1: alternative functions of the digital audio bus inter face on the pcm interface production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 40 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
9.1 audio input and output the audio input circuitry consists of: 2 independent 16-bit high-quality adc channels: programmable as either microphone or line input programmable as either stereo or dual-mono inputs multiplexed with 2 of the digital microphone inputs, see sectio n 9.2.16 each channel is independently configurable to be either single- ended or fully differential each channel has an analogue and digital programmable gain stag e for optimisation of different microphones 6 digital mems microphone channels, of which 4 have independent codec channels and 2 share their codecs with the 2 high-quality audio inputs the audio output circuitry consists of a dual differential clas s a-b output stage. note: CSR8670 bga is designed for a differential audio output. if a s ingle-ended audio output is required, use an external differential to single-ended converter. 9.2 audio codec interface the main features of the interface are: stereo and mono analogue input for voice band and audio band stereo and mono analogue output for voice band and audio band support for stereo digital audio bus standards such as i2s support for iec-60958 standard stereo digital audio bus standar ds, e.g. spdif and aes3 (also known as aes/ebu) support for pcm interfaces including pcm master codecs that req uire an external system clock important note: to avoid any confusion regarding stereo operation this data she et explicitly states which is the left and right channel for audio output. with respect to audio input, software and any registers, channel 0 or channel a represents the left channel and channel 1 or channel b represen ts the right channel. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 41 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
9.2.1 audio codec block diagram g-tw-0005384.6.2 digital mic digital mic digital mic digital mic digital mic digital mic digital codec digital codec digital codec digital codec 16 16 16 16 input f input e input d input c input b input a high-quality adc high-quality adc data mux mux 16 16 data data data data mic_rp mic_rn mic_lp mic_ln clock clock clock clock data clock pio[even] pio[odd] pio[odd] pio[odd] digital codec digital codec clock note: l/r pins on digital microphones pulled up or down on the pcb s t e r e o a u d i o a n d v o i c e b a n d o u t p u t high-quality dac low-pass filter spkr_ln spkr_lp 16 high-quality dac spkr_rn spkr_rp 16 digital circuitry s t e r e o a u d i o , v o i c e b a n d a n d d i g i t a l m i c r o p h o n e i n p u t pio[even] pio[even] low-pass filter digital mic interface digital mic interface digital mic interface figure 9.2: audio codec input and output stages the CSR8670 bga audio codec uses a fully differential architect ure in the analogue signal path, which results in low noise sensitivity and good power supply rejection while eff ectively doubling the signal amplitude. it operates from a dual power supply, vdd_audio for the audio circuits and vdd_a udio_drv for the audio driver circuits. 9.2.2 codec set-up the configuration and control of the adc is through software fu nctions described in appropriate development kit documentation. this section is an overview of the parameters se t up using the software functions. the kalimba dsp communicates its codec requirements to the mcu, and therefore also to the vm, by exchanging messages. messages between the kalimba dsp and the embedded mcu are based on interrupts: 1 interrupt between the mcu and kalimba dsp 1 interrupt between the kalimba dsp and the mcu message content is transmitted using shared memory. there are v m and dsp library functions to send and receive messages; see appropriate development kit documentation for fur ther details. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 42 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
9.2.3 adc figure 9.2 shows the CSR8670 bga consists of 2 high-quality adc s: each adc has a second-order sigma-delta converter. each adc is a separate channel with identical functionality. there are 2 gain stages for each channel, 1 of which is an anal ogue gain stage and the other is a digital gain stage, see section 9.2.5. 9.2.4 adc sample rate selection each adc supports the following pre-defined sample rates, altho ugh other rates are programmable, e.g. 40khz: 8khz 11.025khz 16khz 22.050khz 24khz 32khz 44.1khz 48khz 9.2.5 adc audio input gain figure 9.3 shows that the CSR8670 bga audio input gain consists of: an analogue gain stage based on a pre-amplifier and an analogue gain amplifier, see section 9.2.6 a digital gain stage, see section 9.2.7 g-tw-0005535.4.3 adc pre-amplifier and adc analogue gain: -3db to 42db in 3db steps adc pre-amplifier: 0db, 9db, 21db and 30db adc analogue gain: -3db to 12db in 3db steps adc digital gain: -24db to 21.5db in alternating 2.5db and 3db steps audio input to digital codec system gain = adc pre-amplifie r + adc analogue gain + adc digit al gain figure 9.3: audio input gain 9.2.6 adc pre-amplifier and adc analogue gain CSR8670 bga has an analogue gain stage based on an adc pre-ampl ifier and adc analogue amplifier: the adc pre-amplifier has 4 gain settings: 0db, 9db, 21db and 3 0db the adc analogue amplifier gain is -3db to 12db in 3db steps the overall analogue gain for the pre-amplifier and analogue am plifier is -3db to 42db in 3db steps, see figure 9.3 at mid to high gain levels it acts as a microphone pre-amplifie r, see section 9.2.15 at low gain levels it acts as an audio line level amplifier production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 43 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
9.2.7 adc digital gain a digital gain stage inside the adc varies from -24db to 21.5db , see table 9.2. there is also a fine gain interface with a 9-bit gain setting allowing gain changes in 1/32 steps, for more infomation contact csr. the firmware controls the audio input gain. digital gain selection value adc digital gain setting (db) digital gain selection value adc digital gain setting (db) 0 0 8 -24 1 3.5 9 -20.5 2 6 10 -18 3 9.5 11 -14.5 4 12 12 -12 5 15.5 13 -8.5 6 18 14 -6 7 21.5 15 -2.5 table 9.2: adc audio input gain rate 9.2.8 adc digital iir filter the adc contains 2 integrated anti-aliasing filters: a long iir filter suitable for music (>44.1khz) g.722 filter is a digital iir filter that improves the stop-ban d attenuation required for g.722 compliance (which is the best selection for 8khz / 16khz / voice) for more information contact csr. 9.2.9 dac the dac consists of: 2 fourth-order sigma-delta converters enabling 2 separate chann els that are identical in functionality, as figure 9.2 shows. 2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain stage. 9.2.10 dac sample rate selection each dac supports the following sample rates: 8khz 11.025khz 16khz 22.050khz 32khz 40khz production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 44 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
44.1khz 48khz 96khz 9.2.11 dac digital gain a digital gain stage inside the dac varies from -24db to 21.5db , see table 9.3. there is also a fine gain interface with a 9-bit gain setting enabling gain changes in 1/32 steps, for more information contact csr. the overall gain control of the dac is controlled by the firmwa re. its setting is a combined function of the digital and analogue amplifier settings. digital gain selection value dac digital gain setting (db) digital gain selection value dac digital gain setting (db) 0 0 8 -24 1 3.5 9 -20.5 2 6 10 -18 3 9.5 11 -14.5 4 12 12 -12 5 15.5 13 -8.5 6 18 14 -6 7 21.5 15 -2.5 table 9.3: dac digital gain rate selection 9.2.12 dac analogue gain table 9.4 shows that the dac analogue gain stage consists of 8 gain selection values that represent seven 3db steps. the firmware controls the overall gain control of the dac. its setting is a combined function of the digital and analogue amplifier settings. analogue gain selection value dac analogue gain setting (db) analogue gain selection value dac analogue gain setting (db) 7 0 3 -12 6 -3 2 -15 5 -6 1 -18 4 -9 0 -21 table 9.4: dac analogue gain rate selection production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 45 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
9.2.13 dac digital fir filter the dac contains an integrated digital fir filter with the foll owing modes: a default long fir filter for best performance at 44.1khz. a short fir to reduce latency. a narrow fir (a very sharp roll-off at n yquist) for g.72 2 compliance. b est for 8khz / 16khz. 9.2.14 iec 60958 interface the iec 60958 interface is a digital audio interface that uses bi-phase coding to minimise the dc content of the transmitted signal and enables the receiver to decode the clock information from the transmitted signal. the iec 60958 specification is based on the 2 industry standards: aes3 (also kno wn as aes/ebu) sony and philips interface specification spdif the interface is compatible with iec 60958-1, iec 60958-3 and i ec 60958-4. the spdif interface signals are spdif_in and spdif_out and are shared on the pcm interface pins. the input and output stages of the spdif pins interface to: a 75 coaxial cable with an rca connector, see figure 9.4 an optical link that uses toslink optical components, see figur e 9.5. g-tw-0000211.3.3 spdif_out (pcm_out) 8 9 u4d 10 11 u4e 12 13 u4f 1 3 4 2 conn2 6 5 u4c spdif coaxial pc esd protection c26 150n r15 120r c20 10n r9 150r r8 150r r10 1k r11 1k r16 560r r17 560r r18 560r r19 100k 3v3 4 3 1 2 5 u3 r12 10k 3v3 c22 100n c21 1u r13 10k r14 470k 3 7 1 6 4 5 2 8 d5 tn33 tn34 3v3 spdif_in (pcm_in) figure 9.4: example circuit for spdif interface (co-axial) production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 46 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0000212.3.3 spdif_out (pcm_out) spdif toslink receiver spdif toslink transmitter 3v3 3v3 c24 100n c25 100n l3 47u out 1 gnd 2 vcc 3 nc 4 nc 5 nc 6 nc 7 u6 input 3 gnd 1 vcc 2 nc 4 nc 5 nc 6 nc 7 u5 spdif_in (pcm_in) figure 9.5: example circuit for spdif interface (optical) 9.2.15 microphone input CSR8670 bga contains 2 independent low-noise microphone bias ge nerators. the microphone bias generators are recommended for biasing electret condensor microphones. figure 9.6 shows a biasing circuit for microphones with a sensitivity between about ?40 to ?60db (0db = 1v/pa). where: the microphone bias generators derives their power from vbat (v ia smp_vbat) or vout_3v3 (via smps_3v3) and requires no capacitor on its output. the microphone bias generators maintains regulation within the limits 70a to 2.8ma, supporting a 2ma source typically required by 2 electret condensor microphones. if the microphone sits below these limits, then the microphone output must be pre-loaded with a large valu e resistor to ground. biasing resistors r1 and r2 equal 2.2k. the input impedance at mic_ln, mic_lp, mic_rn and mic_rp is typ ically 6k. c1, c2, c3 and c4 are 100/150nf if bass roll-off is required to limit wind noise on the microphone. r1 and r2 set the microphone load impedance and are normally ar ound 2.2k. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 47 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0005536.3.2 c2 r1 c1 microphone bias (mic_bias_a or mic_bias_b) mic_lp mic_ln mic1 + input amplifier c4 r2 c3 microphone bias (mic_bias_a or mic_bias_b) mic_rp mic_rn mic2 + input amplifier figure 9.6: microphone biasing the microphone bias characteristics include: power supply: CSR8670 bga microphone supply is vbat (via smp_vbat) or vout_3v 3 (via smps_3v3) minimum input voltage = output voltage + drop-out voltage maximum input voltage is 4.25v drop-out voltage: 300mv maximum output voltage: 1.8v or 2.6v tolerance 90% to 110% output current: 70a to 2.8ma no load capacitor required 9.2.16 digital microphone inputs the CSR8670 bga interfaces to 6 digital mems microphones. figur e 9.2 shows that 4 of the inputs have dedicated codec channels and 2 are multiplexed with the high-quality adc channels. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 48 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
figure 9.2 shows that the digital microphone interface on the c sr8670 bga has: clock lines shared between 2 microphone outputs, linked to any even-numbered pio pin as determined by the firmware. note: multiple digital microphones can share the same clock if they a re configured for the same frequency, e.g. 1 clock for 6 digital microphones. data lines shared beween 2 microphone inputs, linked to any odd -numbered pio as determined by the firmware. note: for the digital microphone interface to work in this configurat ion ensure the microphone uses a tristate between edges. the left and right selection for the digital microphones are ap propriately pulled up or down for selection on the pcb. 9.2.17 line input section 9.2.5 states that if the pre-amplifier audio input gain is set at a low gain level it acts as an audio line level amplifier. in this line input mode the input impedance varies f rom 6k to 30k, depending on the volume setting. figure 9.7 and figure 9.8 show 2 circuits for line input operat ion and show connections for either differential or single- ended inputs. g-tw-0005511.2.2 c3 c4 mic_rn mic_rp c1 c2 mic_ln mic_lp figure 9.7: differential input production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 49 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0005512.2.2 c3 c4 mic_rp mic_rn c1 c2 mic_lp mic_ln figure 9.8: single-ended input 9.2.18 output stage the output stage digital circuitry converts the signal from 16- bit per sample, linear pcm of variable sampling frequency to bit stream, which is fed into the analogue output circuitry. the analogue output circuit comprises a dac, a buffer with gain -setting, a low-pass filter and a class ab output stage amplifier. figure 9.9 shows that the output is available as a differential signal between spkr_ln and spkr_lp for the left channel , and between spkr_rn and spkr_rp for the r ight channel. g-tw-0005537.1.1 spkr_lp spkr_ln spkr_rp spkr_rn figure 9.9: speaker output 9.2.19 mono operation mono operation is a single-channel operation of the stereo code c. the left channel represents the single mono channel for audio in and audio out. in mono operation, the righ t channel is the auxiliary mono channel for dual-mono channel operation. in single channel mono operation, disable the other channel to reduce power consumption. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 50 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
9.2.20 side tone in some applications it is nece ssary to implement side tone. th is side tone function involves feeding a properly gained microphone signal in to the dac stream, e.g. earpiece. t he side tone routing selects the version of the microphone signal from before or after the digital gain in the adc interface and adds it to the output signal before or after the digital gain of the dac interface, see figure 9.10 . g-tw-0005375.1.1 side tone route digital input analogue output digital output analogue input digital gain demux mux dac dac interface side tone digital gain adc adc interface side tone route side tone gain figure 9.10: side tone the adc provides simple gain to the side tone data. the gain va lues range from -32.6db to 12.0db in alternating steps of 2.5db and 3.5db, see table 9.5. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 51 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
value sidetone gain value sidetone gain 0 -32.6db 8 -8.5db 1 -30.1db 9 -6.0db 2 -26.6db 10 -2.5db 3 -24.1db 11 0db 4 -20.6db 12 3.5db 5 -18.1db 13 6.0db 6 -14.5db 14 9.5db 7 -12.0db 15 12.0db table 9.5: sidetone gain note: the values of side tone are shown for information only. during standard operation, the application software controls the sidetone gain. the following ps keys configure the side tone hardware: pskey_side_tone_enable pskey_side_tone_gain pskey_side_tone_after_adc pskey_side_tone_after_dac 9.2.21 integrated digital iir filter CSR8670 bga has a programmable digital filter integrated into t he adc channel of the codec. the filter is a 2-stage, second order iir and is for functions such as custom wind noise reduction. the filter also has optional dc blocking. the filter has 10 configuration words: 1 for gain value 8 for coefficient values 1 for enabling and disabling the dc blocking the gain and coefficients are all 12-bit 2's complement signed integer with the format nn.nnnnnnnnnn . note: the position of the binary point is between bit[10] and bit[9], where bit[11] is the most significant bit. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 52 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
for example: 01.1111111111 01.0000000000 00.0000000000 11.0000000000 10.0000000000 = = = = = most positive number, close to 2 1 0 -1 -2 , most negative number equation 9.1 shows the equation for the iir filter. equation 9. 2 shows the equation for when the dc blocking is enabled. the filter is configured, enabled and disabled from the vm via the codecsetiirfiltera and codecsetiirfilterb traps. this requires firmware support. the configuration funct ion takes 10 variables in the following order: 0 1 2 3 4 5 6 7 8 9 : : : : : : : : : : gain b 01 b 02 a 01 a 02 b 11 b 12 a 11 a 12 dc block (1 = enable, 0 = disable) filter, h(z) = gain ( 1+b 01 z ?1 +b 02 z ?2 ) ( 1+a 01 z ?1 +a 02 z ?2 ) ( 1+b 11 z ?1 +b 12 z ?2 ) ( 1+a 11 z ?1 +a 12 z ?2 ) equation 9.1: iir filter transfer function, h(z) filter with dc blocking, h dc (z) = h(z) ( 1?z ?1 ) equation 9.2: iir filter plus dc blocking transfer function, h dc (z) 9.3 pcm interface the audio pcm interface on the CSR8670 bga supports: on-chip routing to kalimba dsp continuous transmission and reception of pcm encoded audio data over bluetooth. processor overhead reduction through hardware support for conti nual transmission and reception of pcm data a bidirectional digital audio interface that routes directly in to the baseband layer of the firmware. it does not pass through the hci protocol layer. hardware on the CSR8670 bga for sending data to and from a sco connection. up to 3 sco connections on the pcm interface at any one time. pcm interface master, generating pcm_sync and pcm_clk. pcm interface slave, accepting externally generated pcm_sync an d pcm_clk. production information this material is subject to csr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 53 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
various clock fo rmats including: long frame sync short frame sync gci timing environments 13-bit or 16-bit linear, 8-bit -law or a-law companded sample formats. receives and transmits on any selection of 3 of the first 4 slo ts following pcm_sync. the pcm configuration options are enabled by setting the ps key pskey_pcm_config32. 9.3.1 pcm interface master/slave when configured as the master of the pcm interface, CSR8670 bga generates pcm_clk and pcm_sync. g-tw-0007827.1.1 128/256/512/1536/2400khz 8/16/32/48khz pcm_out pcm_in pcm_clk pcm_sync figure 9.11: pcm interface master g-tw-0000218.3.3 up to 2400khz 8/48khz pcm_out pcm_in pcm_clk pcm_sync figure 9.12: pcm interface slave 9.3.2 long frame sync long frame sync is the name given to a clocking format that con trols the transfer of pcm data words or samples. in long frame sync, the rising e dge of pcm_sync indicates the s tart of the pcm word. when CSR8670 bga is configured as pcm master, generating pcm_sync and pcm_clk, then pcm_sync is 8 bits long. when CSR8670 bga is config ured as pcm slave, p cm_sync is from 1 cycl e pcm_clk to half the pcm_sync rate. production information this material is subject to csr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 54 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0000219.2.2 pcm_sync pcm_clk pcm_out pcm_in 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 undefined undefined figure 9.13: long frame sync (shown with 8-bit companded sample ) CSR8670 bga samples pcm_in on the falling edge of pcm_clk and t ransmits pcm_out on the rising edge. pcm_out is configurable as high impedance on the falling edge o f pcm_clk in the lsb position or on the rising edge. 9.3.3 short frame sync in short frame sync, the falling edge of pcm_sync indicates the start of the pcm word. pcm_sync is always 1 clock cycle long. g-tw-0000220.2.3 pcm_sync pcm_clk pcm_out pcm_in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 undefined undefined figure 9.14: short frame sync (shown with 16-bit sample) as with long frame sync, CSR8670 bga samples pcm_in on the fall ing edge of pcm_clk and transmits pcm_out on the rising edge. pcm_out is configurable as high imp edance on the falling edge of pcm_clk in the lsb position or on the rising edge. 9.3.4 multi-slot operation more than 1 sco connection over the pcm interface is supported using multiple slots. up to 3 sco connections are carried over any of the first 4 slots. production information this material is subject to csr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 55 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0000221.3.2 long_pcm_sync or short_pcm_sync pcm_clk pcm_out pcm_in 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 do not care do not care figure 9.15: multi-slot operation with 2 slots and 8-bit compan ded samples 9.3.5 gci interface CSR8670 bga is compatible with the gci, a standard synchronous 2b+d isdn timing interface. the 2 64kbps b channels are accessed when this mode is configured. g-tw-0000222.2.3 pcm_sync pcm_clk pcm_out pcm_in 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 do not care do not care b1 channel b2 channel figure 9.16: gci interface the start of frame is indicated by the rising edge of pcm_sync and typically runs at 8khz/16khz. 9.3.6 slots and sample formats CSR8670 bga receives and transmits on any selection of the firs t 4 slots following each sync pulse. slot durations are either 8 or 16 clock cycles: 8 clock cycles for 8-b it sample formats. 16 clocks cycles for 8-b it, 13-bit or 16-b it sample formats. CSR8670 bga supports: 13-bit linear, 16-bit linear and 8-bit -law or a-law sample fo rmats. a sample rate of 8ksa mples/s, 16ksamples/ s or 32ksamples/s. little or big endian bit order. for 16-bit slots, the 3 or 8 unused bits in each slot are fille d with sign extension, padded with zeros or a programmable 3-bit audio attenuation compatible with some codec s. production information this material is subject to csr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 56 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0000223.2.3 pcm_out pcm_out pcm_out pcm_out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sign extension 8-bit sample 8-bit sample zeros padding sign extension 13-bit sample 13-bit sample audio gain a 16-bit slot with 8-bit companded sample and sign extension selected. a 16-bit slot with 8-bit companded sample and zeros padding selected. a 16-bit slot with 13-bit linear sample and sign extension selected. a 16-bit slot with 13-bit linear sample and audio gain selected. figure 9.17: 16-bit slot length and sample formats 9.3.7 additional features CSR8670 bga has a mute facility that forces pcm_out to be 0. in master mode, CSR8670 bga is compatible with some codecs which control power down by forcing pcm_sync to 0 w hile keeping pcm_clk running. production information this material is subject to csr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 57 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
9.3.8 pcm timing information symbol parameter min typ max unit f mclk pcm_clk frequency 4mhz dds generation. selection of frequency is programmable. see section 9.3.10. - 128 - khz 256 512 48mhz dds generation. selection of frequency is programmable. see section 9.3.10. 2.9 - - khz - pcm_sync frequency for sco connection - 8 - khz t mclkh (a) pcm_clk high 4mhz dds generation 980 - - ns t mclkl (a) pcm_clk low 4mhz dds generation 730 - - ns - pcm_clk jitter 48mhz dds generation - - 21 ns pk-pk t dmclksynch delay time from pcm_ clk high to pcm_sync high - - 20 ns t dmclkpout delay time from pcm_clk high to valid pcm_out - - 20 ns t dmclklsyncl delay time from pcm_clk low to pcm_sync low (long frame sync only) - - 20 ns t dmclkhsyncl delay time from pcm_ clk high to pcm_sync low - - 20 ns t dmclklpoutz delay time from pcm_clk low to pcm_out high impedance - - 20 ns t dmclkhpoutz delay time from pcm_ clk high to pcm_out high impedance - - 20 ns t supinclkl set-up time for pcm_in valid to pcm_clk low 20 - - ns t hpinclkl hold time for pcm_clk low to pcm_in invalid 0 - - ns table 9.6: pcm master timing (a) assumes normal system clock opera tion. figures vary during low- power modes, when system clock speeds are reduced. production information this material is subject to csr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 58 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0000224.2.3 pcm_sync pcm_clk pcm_out pcm_in msb (lsb) lsb (msb) msb (lsb) lsb (msb) f mlk t mclkh t mclkl t supinclkl t dmclksynch t dmclkpout t hpinclkl t dmclklsyncl t dmclkhsyncl t dmclklpoutz t dmclkhpoutz t r ,t f figure 9.18: pcm master timing long frame sync g-tw-0000225.3.3 pcm_sync pcm_clk pcm_out pcm_in msb (lsb) lsb (msb) msb (lsb) lsb (msb) f mlk t mclkh t mclkl t supinclkl t t dmclkpout t hpinclkl dmclkhsyncl t dmclklpoutz t dmclkhpoutz t r ,t f t dmclksynch figure 9.19: pcm master timing short frame sync production information this material is subject to csr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 59 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
symbol parameter min typ max unit f sclk pcm clock frequency (slave mode: input) 64 - (a) khz f sclk pcm clock freque ncy (gci mode) 128 - (b) khz t sclkl pcm_clk low time 200 - - ns t sclkh pcm_clk high time 200 - - ns t hsclksynch hold time from pcm_clk low to pcm_sync high 2 - - ns t susclksynch set-up time for pcm_sy nc high to pcm_clk low 20 - - ns t dpout delay time from pcm_sync or pcm_clk, whichever is later, to valid pcm_out data (long frame sync only) - - 20 ns t dsclkhpout delay time from clk high to pcm_out valid data - - 15 ns t dpoutz delay time from pcm_sync or pcm_clk low, whichever is later, to pcm_out data line high impedance - - 15 ns t supinsclkl set-up time for pcm_in valid to clk low 20 - - ns t hpinsclkl hold time for pcm_clk low to pcm_in invalid 2 - - ns table 9.7: pcm slave timing (a) max frequency is the frequency def ined by pskey_pcm_min_cpu_clo ck (b) max frequency is twice the freq uency defined by pskey_pcm_min_c pu_clock production information this material is subject to csr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 60 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0000226.3.2 pcm_clk pcm_sync pcm_out pcm_in msb (lsb) lsb (msb) f sclk t sclkh t tsclkl t hsclksynch t susclksynch t dpout t dsclkhpout t dpoutz t dpoutz t supinsclkl t hpinsclkl t r ,t f lsb (msb) msb (lsb) figure 9.20: pcm slave timing long frame sync g-tw-0000227.3.2 pcm_clk pcm_sync pcm_out pcm_in msb (lsb) lsb (msb) f sclk t sclkh t tsclkl t hsclksynch t susclksynch t dpoutz t dpoutz t supinsclkl t hpinsclkl t r ,t f lsb (msb) msb (lsb) t dsclkhpout figure 9.21: pcm slave timing short frame sync 9.3.9 pcm_clk and pcm_sync generation CSR8670 bga has 2 methods of generating pcm_clk and pcm_sync in master mode: production information this material is subject to csr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 61 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
generating these signals by dds from CSR8670 bga internal 4mhz clock. using t his mode limits pcm_clk to 128, 256 or 512khz and pcm_sync to 8khz. generating these signals by dds from an internal 48mhz clock, w hich enables a greater range of frequencies to be generated with low jitter but consumes more p ower. to select this second method set bit 48m_pcm_clk_gen_en in pskey_pcm_co nfig32. when in this mode and with long frame sync, the length of pcm_sync is either 8 or 16 cycles of pcm_clk, determi ned by long_length_sync_en in pskey_pcm_config32. equation 9.3 describes pcm_clk frequency when generated from th e internal 48mhz clock: f= cnt_rate cnt_limit 24mhz equation 9.3: pcm_clk frequency generated using the internal 48 mhz clock set the frequency of pcm_sync rela tive to pcm_clk using equatio n 9.4: f= pcm_clk sync_limit 8 equation 9.4: pcm_sync frequency relative to pcm_clk cnt_rate, cnt_limit and sync_li mit are set using pskey_pcm_low_ jitter_config. as an example, to generate pcm_clk at 512khz with pcm_sync at 8khz, set pskey_pcm _low_jitter_config to 0x08080177 . 9.3.10 pcm configuration configure the pcm by using pskey_pcm_co nfig32 and pskey_pcm_use _low_jitter_mo de, see your ps key file. the default for pskey_pcm_ config32 is 0 x00800000, i.e. first slot following sync is active, 13-bit linear voice format, long frame sync and interface master gener ating 256khz pcm_clk from 4mhz internal clock with no tristate of pcm_out. 9.4 digital audio interface (i2s) the digital audio interface supports the industry standard form ats for i2s, left-justified or right-justified. the interface shares the same pins as the pcm interface, which means each aud io bus is mutually exclusive in its usage. table 9.8 lists these alternative functions. figure 9.22 shows the ti ming diagram. pcm interface i2s interface pcm_out sd_out pcm_in sd_in pcm_sync ws pcm_clk sck table 9.8: alternative functions of the digital audio bus inter face on the pcm interface configure the digital audio interface using pskey_digital_audio _config, see the ps key file. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 62 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0000230.3.2 ws sck sd_in/out ws sck sd_in/out ws sck sd_in/out lsb msb lsb msb lsb msb lsb msb lsb left -justified mode right -justified mode left channel right channel right channel left channel left channel right channel msb lsb msb i 2 s mode figure 9.22: digital audio interface modes the internal representation of audio samples within CSR8670 bga is 16-bit and data on sd_out is limited to 16- bit per channel. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 63 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
symbol parameter min typ max unit - sck frequency - - 6.2 mhz - ws frequency - - 96 khz t ch sck high time 80 - - ns t cl sck low time 80 - - ns table 9.9: digital audio interface slave timing symbol parameter min typ max unit t ssu ws valid to sck high set-up time 20 - - ns t sh sck high to ws invalid hold time 2.5 - - ns t opd sck low to sd_out valid delay time - - 20 ns t isu sd_in valid to sck high set-up time 20 - - ns t ih sck high to sd_in invalid hold time 2.5 - - ns table 9.10: i2s slave mode timing g-tw-0000231.2.2 sd_out sd_in t t t t t t ws(input) sck(input) ch opd ih sh ssu cl isu t figure 9.23: digital audio interface slave timing production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 64 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
symbol parameter min typ max unit - sck frequency - - 6.2 mhz - ws frequency - - 96 khz table 9.11: digital audio interface master timing symbol parameter min typ max unit t spd sck low to ws va lid delay time - - 39.27 ns t opd sck low to sd_out valid delay time - - 18.44 ns t isu sd_in valid to sck high set-up time 18.44 - - ns t ih sck high to sd_in invalid hold time 0 - - ns table 9.12: i2s master mode timing parameters, ws and sck as ou tputs g-tw-0000232.2.2 ws(output) sck(output) sd_out sd_in t isu t ih t opd t spd figure 9.24: digital audio interface master timing production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 65 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
10 wlan coexistence interface dedicated hardware is provided to implement a variety of wlan c oexistence sch emes. there is support for: channel skipping afh priority signalling channel signalling host passing of channel instructions planned support for wlan coexistence schemes includes: unity-3 unity-3e unity+ for more information on wlan coexistence schemes supported on c sr8670 bga see software release note or contact csr. for more information on wlan coexistence schemes see bluetooth and ieee 802.11 b/g co -existence solutions overview . production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 66 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
11 power control and regulation for greater power efficiency the CSR8670 bga contains 2 switch- mode regulators: 1 generates a 1.80v supply rail with an output current of 185ma , see section 11.1. 1 generates a 1.35v supply rail with an output current of 160ma , see section 11.2. combining the 2 switch-mode regulators in parallel generates a single 1.80v supply rail with an output current of 340ma, see section 11.3. CSR8670 bga contains 4 ldo linear regulators: 3.30v bypass regulator, see section 11.4. 0.80v to 1.25v vdd_dig linear regulator, see section 11.5. 1.35v vdd_aux linear regulator, see section 11.6. 1.35v vdd_ana linear regulator, see section 11.7. the recommended configurations for power control and regulation on the CSR8670 bga are: 3 switch-mode configurations: a 1.80v and 1.35v dual-s upply rail system usi ng the 1.80v and 1 .35v switch-mode regulators, see figure 11.1. this is the default power control and regulation c onfiguration for the CSR8670 bga. a 1.80v single-supply rail system using the 1.80v switch-mode r egulator. a 1.80v parallel -supply rail system for h igher current s using t he 1.80v and 1.35v switch-mode regulators with combined outputs, see figure 11.2. a linear configuration using an external 1.8v rail omitting all regulators table 11.1 shows settings for the recommended configurations fo r power control and regulation on the CSR8670 bga. supply configuration regulators supply rail switch-mode vdd_aux linear regulator vdd_ana linear regulator 1.8v 1.35v 1.8v 1.35v dual-supply smps on on off off smps smps single-supply smps on off on on smps ldo parallel- supply smps on on on on smps ldo external 1.8v linear supply off off on on external ldo table 11.1: recommended configurations for power control and re gulation for more information on CSR8670 bga power supply configuration see configuring the power supplies on CSR8670 application note. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 67 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0005545.7.2 mic bias 1 charge reference mic_bias_a bypass linear regulator 300ma charger 50 to 200ma reference 1. 8v switch-mode regulator 185ma 1.35v switch-mode regulator 160ma vchg vbat vbat_sense mic bias 2 mic_bias_b lx_1v35 lx_1v8 vout_3v3 3.3v 1.35v 1. 8v audio driver audio core vdd_audio_drv vdd_audio audio circuits vdd_aux regulator vdd_ana regulator e-flash i/o analogue and auxiliary bluetooth smps_1v8_sense smps_1v35_sense sense in out out vdd_aux sense out out vdd_ana sense vdd_bt_radio in sense auxiliary circuits vdd_bt_lo smp_vbat in in smps_3v3 digital core circuits vdd_dig regulator out sense in vdd_dig_eflash vregin_dig vdd_eflash_1v8 vdd_usb en en en en en en out sense vregenable vdd_pads_1 vdd_pads_2 vdd_pads_3 vdd_aux_1v8 figure 11.1: 1.80v and 1.35v dual-supply switch-mode system con figuration production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 68 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0005546.5.2 mic bias 1 charge reference mic_bias_a bypass linear regulator 300ma charger 50 to 200ma reference 1. 8v switch-mode regulator 340ma 1.35v switch-mode regulator vchg vbat vbat_sense mic bias 2 mic_bias_b lx_1v35 lx_1v8 vout_3v3 3.3v 1.35v 1. 8v audio driver audio core vdd_audio_drv vdd_audio audio circuits vdd_aux regulator vdd_ana regulator e-flash i/o analogue and auxiliary bluetooth smps_1v8_sense smps_1v35_sense sense in out out vdd_aux sense out out vdd_ana sense vdd_bt_radio in sense auxiliary circuits vdd_bt_lo smp_vbat in in smps_3v3 digital core circuits vdd_dig regulator out sense in vdd_dig_eflash vregin_dig vdd_eflash_1v8 vdd_usb en en en en en en out sense vregenable vdd_pads_1 vdd_pads_2 vdd_pads_3 vdd_aux_1v8 figure 11.2: 1.80v parallel-supply switch-mode system configura tion production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 69 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0008349.1.1 mic bias 1 charge reference mic_bias_a bypass linear regulator 300ma charger 50 to 200ma reference 1.8v switch-mode regulator 340ma 1.35v switch-mode regulator vchg vbat vbat_sense mic bias 2 mic_bias_b lx_1v35 lx_1v8 vout_3v3 3. 3v 1. 35v 1.8v audio driver audio core vdd_audio_drv vdd_audio audio circuits vdd_aux regulator vdd_ana regulator e-flash i/o analogue and auxiliary bluetooth smps_1v8_sense smps_1v35_sense sense in out out vdd_aux sense out out vdd_ana sense vdd_bt_radio in sense auxiliary circuits vdd_bt_lo smp_vbat in in smps_3v3 digital core circuits vdd_dig regulator out sense in vdd_dig_eflash vregin_dig vdd_eflash_1v8 vdd_usb en en en en en en out sense vregenable vdd_pads_1 vdd_pads_2 vdd_pads_3 vdd_aux_1v8 figure 11.3: external 1.8v system configuration production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 70 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
11.1 1.8v switch-mode regulator csr recommends the integrated switch-mode regulator to power th e 1.80v supply rail. figure 11.4 shows that an external lc filter circuit of a low-r esistance series inductor, l1 (4.7h), followed by a low esr shunt capacitor, c3 (2.2f), are required between the lx_1v 8 terminal and the 1.80v supply rail. a connection between the 1.80v supply rail and the smps_1v8_sense pin is req uired. g-tw-0005542.3.2 smps_1v8_sense lx_1v8 1 .8 v switch -mode regulator sense lx l1 4.7h c3 2.2f 1.8v supply rail vss_smps_1v8 smp_vbat smps_3v3 to 1.35 v switch -mode regulator input c1 2.2f c2 2.2f vbat vout_3v3 figure 11.4: 1.8v switch-mode regulator output configuration ensure the series resistance of the tracks is minimised between the regulator input, s mp_vbat and smps_3v3, ground terminals, the filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and low supply ripple. ensure a solid ground plane between c1, c2, c3 and vss_smps_1v8 . also minimise the collective parasitic capacitance on the track between lx_1v8 and the inductor l1, to maximise efficiency. for the regulator to meet the specifications in section 15.3.1. 1 requires a total resistance of <1.0 (<0.5 recommended) for the following: the track between the battery and smp_vbat. the track between lx_1v8 and the inductor. the inductor, l1, esr. the track between the inductor, l1, and the sense point on the 1.80v supply rail. the following enable the 1.80v switch-mode regulator: vregenable pin the CSR8670 bga firmware with reference to pskey_psu_enables vchg pin the switching frequency is adjustable by setting an offset from 4.00mhz using pskey_smps_freq_offset, which also affects the 1.35v switch-mode regulator. when the 1.80v switch-mode regulator is not required, leave unc onnected: the regulator input smp_vbat and smps_3v3 the regulator output lx_1v8 11.2 1.35v switch-mode regulator csr recommends the integrated switch-mode regulator to power th e 1.35v supply rail. figure 11.5 shows that an external lc filter circuit of a low-r esistance series inductor l1 (4.7h), followed by a low esr shunt capacitor, c3 (4.7f), are required between the lx_1v 35 terminal and the 1.35v supply rail. a connection between the 1.35v supply rail and the smps_1v35_sense pin is re quired. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 71 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0005543.4.2 smps_1v35_sense lx_1v35 1 .35v switch- mode regulator sense lx l1 4.7h c3 4.7f 1.35v supply rail vss_smps_1v35 smp_vbat smps_3v3 to 1. 8v switch -mode regulator input c1 2.2f c2 2.2f vbat vout_3v3 figure 11.5: 1.35v switch-mode regulator output configuration ensure the series resistance of the tracks is minimised between the regulator input, s mp_vbat and smps_3v3, ground terminals, the filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and low supply ripple. ensure a solid ground plane between c1, c2, c3 and vss_smps_1v3 5. also minimise the collective parasitic capacitance on the track between lx_1v35 and the inductor l1, to maximise efficiency. for the regulator to meet the specifications in section 15.3.2. 1 requires a total resistance of <1.0 (<0.5 recommended) for the following: the track between the battery and smp_vbat. the track between lx_1v8 and the inductor. the inductor, l1, esr. the track between the inductor, l1, and the sense point on the 1.35v supply rail. the following enable the 1.35v switch-mode regulator: vregenable pin the CSR8670 bga firmware with reference to pskey_psu_enables vchg pin the switching frequency is adjustable by setting an offset from 4.00mhz using pskey_smps_freq_offset, which also affects the 1.80v switch-mode regulator. when the 1.35v switch-mode regulator is not required, leave unc onnected: the regulator input smp_vbat and smps_3v3 the regulator output lx_1v35 11.3 1.8v and 1.35v switch-m ode regulators combined for applications that require a single 1.80v supply rail with h igher currents csr recommends combining the outputs of the integrated 1.80v and 1.35v switch-mode regulators in par allel to power a single 1.80v supply rail, see figure 11.6. figure 11.6 shows that an external lc filter circuit of a low-r esistance series inductor l1 (4.7h), followed by a low esr shunt capacitor, c3 (2.2f), are required between the lx_1v 8 terminal and the 1.80v supply rail. a connection between the 1.80v supply rail and the smps_1v8_sense pin is req uired and the smps_1v35_sense pin is grounded. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 72 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0005544.3.2 smps_1v8_sense lx_1v8 1 .8 v switch -mode regulator sense lx l1 4.7h c3 2.2f 1.8v supply rail vss_smps_1v8 smps_1v35_sense lx_1v35 1.35v switch- mode regulator sense lx vss_smps_1v35 smp_vbat smps_3v3 c1 2.2f c2 2.2f vbat vout_3v3 figure 11.6: 1.8v and 1.35v switch-mode regulators outputs para llel configuration ensure the series resistance of the tracks is minimised between the regulator input smp_vbat and smps_3v3, ground terminals, the filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and low supply ripple. ensure a solid ground plane between c1, c2, c3, vss_smps_1v8 an d vss_smps_1v35. also minimise the collective parasitic capacitance on the track between lx_1v8, lx_1v35 and the inductor l1, to maximise efficiency. for the regulator to meet the specifications in section 15.3.1. 2 requires a total resistance of <1.0 (<0.5 recommended) for the following: the track between the battery and smp_vbat. the track between lx_1v8, lx_1v35 and the inductor. the inductor l1, esr. the track between the inductor, l1, and the sense point on the 1.80v supply rail. the following enable the 1.80v switch-mode regulator: vregenable pin the CSR8670 bga firmware with reference to pskey_psu_enables vchg pin the switching frequency is adjustable by setting an offset from 4.00mhz using pskey_smps_freq_offset. when the 1.80v switch-mode regulator is not required, leave unc onnected: the regulator input smp_vbat and smps_3v3 the regulator output lx_1v8 11.4 bypass ldo linear regulator the integrated bypass ldo linear regulator is available as a 3. 30v supply rail and is an alternative supply rail to the battery supply. this is especially useful when the battery has no charge and the CSR8670 bga needs to power up. the input voltage should be between 4.75 / 3.1v and 5.75v. the maximum current from this regulator is 250ma. note: the integrated bypass ldo linear regulator can operates down to 3.0v with a reduced performance. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 73 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
externally decouple the output of this regulator using a low es r mlc capacitor of a minimum 2.2f to the vout_3v3 pin. with careful pcb layout this bypass capacitor can be share d with smps_3v3. the output voltage is switched on when vchg gets above 3.0v. 11.5 low-voltage vdd_dig linear regulator the integrated low-voltage vdd_dig linear regulator is availabl e to power a 0.80v to 1.25v supply rail which includes the digital circuits on CSR8670 bga. the input voltage range is between 1.30v and 1.95v. the maximum current from this regulator is 80ma. externally decouple the output of this regulator using a low es r mlc capacitor of 470nf to the vdd_dig pin for optimum phase margin. the output voltage is enabled by vregenable and the low-voltage vdd_dig linear regulator must be on to run software code. 11.6 low-voltage vdd_aux linear regulator the integrated low-voltage vdd_aux linear regulator is availabl e to power a 1.35v auxiliary supply rail (when the 1.35v switch-mode regulator is not used) which includes the ana logue circuits on CSR8670 bga. the input voltage should be between 1.70v and 1.95v. the maximum current from thi s regulator is 5ma. externally decouple the output of this regulator using a low es r mlc capacitor of a minimum 470nf to the vdd_aux pin. this regulator is enabled by taking vregenable or vchg high and also the software controls the regulator enable/ disable through pskey_psu_enables. for safety, the initial output voltage of the low-voltage vdd_a ux linear regula tor is 1.25v. 11.7 low-voltage vdd_ana linear regulator the integrated low-voltage vdd_ana linear regulator is availabl e to power an optional 1.35v analogue supply rail which includes the analogue circuits on CSR8670 bga. the input voltage should be between 1.70v and 1.95v. the maximum current from this regulator is 60ma. if this regulator is required, externally decouple the output o f this regulator using a 2.2f low esr mlc capacitor to the vdd_ana pin. for more information contact csr. the software cont rols the regulator enab le/disable through pske y_psu_enables. 11.8 voltage regulator enable when using the the integrated regulators the voltage regulator enable pin, vregenable, enables the CSR8670 bga and the following regulators: 1.8v switch-mode regulator 1.35v switch-mode regulator low-voltage vdd_dig linear regulator low-voltage vdd_aux linear regulator the vregenable pin is active high, with a weak pull-down. CSR8670 bga boots-up when the voltage regulator enable pin is p ulled high, enabling the regulators. the firmware then latches the regulators on, i t is then permitted to release the voltage regulator enable pin. the status of the vregenable pin is available to firmware throu gh an internal connection. vregenable also works as an input line. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 74 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
11.9 external regulators and power sequencing csr recommends that the integrated regulators supply the csr867 0 bga and it is configured based on the information in this data sheet. if any of the supply rails for the CSR8670 bga are supplied fro m an external regulator, then it should match or be better than the internal regulator available on CSR8670 bga. fo r more information see regu lator characteristics in section 15. note: the internal regulators described in section 11.1 to section 11 .7 are not recommended for external circuitry other than that shown in section 13. for information about power sequencing of external regulators t o supply the CSR8670 bga contact csr. 11.10 reset, rst# CSR8670 bga is reset f rom several sources: rst# pin power-on reset usb charger attach reset uart break character software configured watchdog timer the rst# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. csr recommends applying rst# for a period >5ms. the power-on reset occurs when: the vdd_dig supply falls below typically 0.97v or the vdd_aux_1v8 supply falls below typically 1.46v and is released when: vdd_dig rises above typically 1.10v or vdd_aux_1v8 rises above typically 1.65v at reset the digital i/o pins are set to inputs for bidirection al pins and outputs are set to tristate. following a reset, CSR8670 bga assumes the maximum xt al_in frequency, which ensure s that the int ernal clocks ru n at a safe (low) frequency until CSR8670 bga is configured for the actual xtal_in frequency. if n o clock is present at xtal_in, the oscillator in CSR8670 bga free runs, again at a sa fe frequency. 11.10.1 digital pin states on reset table 11.2 shows the pin states of CSR8670 bga on reset. pu and pd default to weak values unless specified otherwise. pin name / group i/o type full chip reset usb_dp digital bidirectional n/a usb_dn digital bidirectional n/a uart_rx digital bidirectional with pu strong pu production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 75 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
pin name / group i/o type full chip reset uart_tx digital bidirectional with pu weak pu uart_cts digital bidirectional with pd weak pd uart_rts digital bidirectional with pu weak pu spi_cs# digital input with pu strong pu spi_clk digital input with pd weak pd spi_miso digital tristate output with pd weak pd spi_mosi digital input with pd weak pd pcm_in digital bidirectional with pd weak pd pcm_out digital bidirectional with pd weak pd pcm_sync digital bidirectional with pd weak pd pcm_clk digital bidirectional with pd weak pd rst# digital input with pu strong pu pio[15:0] digital bidirectional with pd weak pd qspi_flash_io[3:0] digital bidirectional with pd strong pd qspi_sram_cs# digital bidirectional with pu strong pu qspi_flash_cs# digital bidirectional with pu strong pu qspi_sram_clk digital bidirectional with pd strong pd qspi_flash_clk digital bidirectional with pd strong pd table 11.2: pin states on reset 11.10.2 status after reset the status of CSR8670 bga after a reset is: warm reset: baud rate and ram data remain available cold reset: baud rate and ram data not available 11.11 automatic reset protection CSR8670 bga includes an automatic reset protection circuit whic h restarts/resets CSR8670 bga when an unexpected reset occurs, e.g. esd strike or lowering of rst#. t he automatic reset protection circuit enables resets from the vm without the requirement for external circuitry. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 76 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
12 battery charger 12.1 battery charger hardware operating modes the default mode for the CSR8670 bga battery charger is off. th e battery charger hardware is enabled by the vm, see section 12.3, this ensures the battery charger remains in a safe state. when enabled, the battery charger has 4 further operating modes: trickle charge fast charge standby: fully charged or float charge error: charging input voltage, vchg, is too low the battery charger operating mode is determined by the battery voltage and current, see table 12.1 and figure 12.1. for charging higher capacity batteries the CSR8670 bga has an e xternal mode that uses an external pass transistor, see section 12.5. mode battery charger enabled vbat_sense off no x trickle charge yes >0 and v fast and (v float - v hyst ) error yes >(vchg - 50mv) table 12.1: battery charger operating modes determined by batte ry voltage and current (a) i term is 10% of i fast for a given i fast setting production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 77 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
figure 12.1 shows the mode-to-mode transition voltages. these v oltages are fixed and calibrated by csr, see section 12.2. the transition between modes can occur at any tim e. g-tw-0005583.3.2 battery voltage charge current v fast i fast i term v hyst i trickle v float trickle charge mode fast charge mode constant current fast charge mode constant voltage standby mode figure 12.1: battery charger mode-to-mode transition diagram 12.1.1 off mode in the off mode the battery charger is fully disabled and draws no active current on any of its terminals. 12.1.2 trickle charge mode in the trickle charge mode, wh en the voltage on vbat_sense is l ower than the v fast threshold, a current of approximately 10% of the fast charge current, i fast , is sourced from the vbat pin. the v fast threshold detection has hysteresis to prevent the charger from oscillating between modes. current drawn from the vchg input is the sum of the current sou rced into the battery, i vchg , plus an overhead of no more than 3.5ma. 12.1.3 fast charge mode when the voltage on vbat_sense is g reater than v fast , the current sourced from the vbat pin increases to i fast . i fast is between 10ma and 200ma set by ps key or a vm trap. in addit ion, i fast is calibrated in production test to correct for process variatio n in the charger circuit. the current is held constant at i fast until the voltage at vbat_sense reaches v float , then the charger reduces the current sourced to maintain a constant voltage on the vbat_sens e pin. when the current sourced is below the termination current, i term , the charging stops and the charger enters standby mode. i term is typically 10% of the fast charge current. 12.1.4 standby mode when the battery is fully charged, the charger enters standby m ode, and battery charging stops. the battery voltage on the vbat_sense pi n is monitored, and wh en it drops below a t hreshold set at v hyst below the final charging voltage, v float , the charger re-enters fast charge mode. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 78 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
12.1.5 error mode the error mode is not entered during normal operation of the cs r8670 bga. the charger enters the error mode when the voltage on the vchg pin is too low to operate the char ger correctly. the charger enters the error mode when the voltage on vbat_sense is greater than vchg - 50mv (typ ical). the battery charger does not require a reset to take it out of the error mode. 12.2 battery charger trimming and calibration the battery charger default trim values are written by csr into internal flash when each ic is characterised. csr provides various ps keys for overriding the default trims, see section 12.4. 12.3 vm battery charger control the vm charger code has overall supervisory control of the batt ery charger and is responsible for: responding to charger power connection/disconnection events monitoring the temperature of the battery monitoring the temperature of t he die to protect against silico n damage monitoring the time spent in the various charge states enabling/disabling the charger circuitry based on the monitored information driving the user visible charger status led(s) 12.4 battery charger firmware and ps keys the battery charger firmware sets up the charger hardware based on the ps key settings and call traps from the vm charger code. it also performs the initial analogue trimming . settings for the charger current depend on the battery capacity and type, which are set by the user in the ps keys. for more information on the CSR8670 bga, including details on s etting up, calibrating, trimming and the ps keys, see lithium polymer battery charger calibration and operation for c sr8670 application note. 12.5 external mode the external mode is for charging higher capacity batteries usi ng an external pass device. the current is controlled by sinking a varying current into the chg_ext pin, and the curr ent is determined by measuring the voltage drop across a resistor, r sense , connected in series with the external pass device, see figure 12.2. the voltage drop is determined by lookin g at the difference b etween the vbat_sense and vbat pins. the v oltage drop across r sense is typically 200mv. the value of the external series resistor determines the charger current. this current can be trimmed with a ps key. in figure 12.2, r1 (220m) and c1 (4.7f) form a rc snubber tha t is required to maintain stability across all battery esrs. the battery esr must be <1.0 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 79 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0005585.2.3 vchg chg_ext vbat_sense vbat bat 1 li+ cell r sense tr 1 external pass device r1 220m ? c1 4.7 w) )ljxuh%dwwhu\&kdujhu([whuqdo0rgh7\slfdo&rqiljxudwlr q 3urgxfwlrq,qirupdwlrq 7klvpdwhuldolvvxemhfwwr& 65
vqrqglvforvxuhdjuhhphqw k&dpeulgjh6lolfrq 5dglr/lplwhg 3djhri &6'63 zzzfvufrp CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
13 example application schematic g-tw-0004754.9.3 2u2 c4 bt rx / tx out 4 in 1 gnd 2 gnd 3 bt filter 2.45ghz u2 4u7 l1 2u2 c3 vbus vbat 26mhz xt1 1v8_smps 330r r8 green d4 mfb s1 li+ cell vbat 3.7v con2 with protection circuit built in 16r / 32r 16r / 32r t h g i r t f e l vbat f2 s4 f3 s3 f4 s2 red d3 blue d2 330r r7 220r r6 vol- s6 vol+ s5 pio_10 pio_9 pio_0 pio_1 pio_2 led_0 led_1 led_2 leds aios spi pcm / i2s / spdif 100k (1%) r5 100k therm1 aio_1 external thermistor lithium polymer battery usb vbus gnd 5 id 4 d+ 3 d- 2 vbus 1 gnd 6 gnd 7 usb mini-b con1 usb interface usb_p usb_n pio_3 470n c12 place under or close to battery 100n c5 2u2 c2 1v8_smps 2u2 c1 8kv esd protection on chip uart 15p c10 4u7 c8 4u7 l2 1v35_smps 10n c11 pios serial flash / sram 15nh l4 15p c19 2u2 c14 mic b mic a 15nh l5 15p c20 100n c15 2k2 r3 100n c16 100n c17 100n c18 2k2 r4 10n c6 3v3_usb 50r 50r 10n c7 3 1 2 bcx51 q1 vbus chg_ext vbat_sense vbat optional external fast charge 400mr configures circuit for 500ma bat54c d1 vbus leds and buttons 1% 400mr r1 4u7 c13 220mr r2 resistor sets fast charge current rc required to compensate for battery resistance place close to r1 above vbat 3v3_usb 2u2 c9 vout_3v3 f12 vdd_pads_1 k1 vss_bt_lo_aux b2 vss_bt_radio a4 uart_cts l3 uart_rx m2 pio[16] / uart_rts k3 uart_tx m3 pio[5] l7 pio[2] m5 pio[6] m6 pio[1] l5 pio[4] k8 pio[19] / pcm_sync h2 pio[20] / pcm_clk g2 pio[7] k9 rst# l1 pio[3] k6 xtal_in c1 mic_lp a10 bt_rf a3 CSR8670 bga xtal_out b1 pio[0] l4 aio[1] d1 spi_mosi g3 spi_miso l2 spi_cs# m1 aio[0] c4 mic_rp c7 mic_ln a11 mic_rn c8 pio[9] / nc l10 pio[8] / nc l8 pio[11] l9 pio[13] j10 pio[12] k10 pio[14] m7 pio[10] m8 vdd_pads_2 k7 vss_audio c9 mic_bias_a a9 au_ref b9 vss_audio_drv b6 spkr_rn a7 spkr_rp b7 spkr_ln c6 spkr_lp c5 vregenable e10 vchg g12 chg_ext f11 vbat_sense h11 vbat h12 lx_1v8 j12 bypass reg charger po[30] / led[1] k5 po[29] / led[0] k4 po[31] / led[2] m4 mic bias spi_clk e1 pio[17] / pcm_in f1 pio[18] / pcm_out h3 usb_p m9 usb_n m10 vss_smps_1v8 j11 vdd_eflash_1v8 j1 nc k2 nc j2 nc j3 mic_bias_b b8 mic bias nc f6 1v8 smps 1v35 smps vss_smps_1v35 m12 nc g6 nc h1 nc g1 cap_sense_5 f2 cap_sense_4 f3 cap_sense_3 e3 cap_sense_2 e2 cap_sense_1 d3 cap_sense_0 d2 vdd_audio a8 vdd_bt_radio a5 vdd_ana c2 vdd_aux c3 aux ldo ana ldo 1v35 1v35 (optional) lx_1v35 l12 smps_1v35_sense m11 vdd_aux_1v8 a1 1v35 vdd_bt_lo a2 vdd_dig_eflash e12 dig ldo 0v85 - 1v20 vregin_dig e11 pio[15] l6 pio[25] / qspi_flash_io0 c11 pio[26] / qspi_flash_io1 b11 pio[27] / qspi_flash_io2 c10 pio[28] / qspi_flash_io3 d12 pio[23] / qspi_flash_cs# d11 pio[21] / qspi_flash_clk c12 vdd_pads_3 a12 vss_dig g10 vss_dig g7 smps_3v3 k11 smp_vbat k12 vdd_usb l11 vdd_audio_drv a6 nc b4 nc b3 vss_bt_radio b5 vss_dig f7 vss_dig d10 vss_dig h10 pio[24] / qspi_sram_cs# b10 pio[22] / qspi_sram_clk b12 smps_1v8_sense f10 vchg g11 1v8_smps production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 81 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
14 example application using differe nt power supply configurations g-tw-0008745.1.2 470n c8 100n c2 100n c1 15p c5 2u2 c6 470n c4 1v35_ana 2u2 c3 out 2 in 4 gnd 1 gnd 3 2.45ghz u2 26mhz x1 bt rx / tx r 0 5 r 0 5 ana ldo requires 2.2uf on its input 2.2uf required for ana ldo smps_sense_1v35 must be connected to gnd turn off both smps in pskey vout_3v3 f12 vdd_pads_1 k1 vss_bt_lo_aux b2 vss_bt_radio a4 uart_cts l3 uart_rx m2 pio[16] / uart_rts k3 uart_tx m3 pio[5] l7 pio[2] m5 pio[6] m6 pio[1] l5 pio[4] k8 pio[19] / pcm_sync h2 pio[20] / pcm_clk g2 pio[7] k9 rst# l1 pio[3] k6 xtal_in c1 mic_lp a10 bt_rf a3 CSR8670 bga xtal_out b1 pio[0] l4 aio[1] d1 spi_mosi g3 spi_miso l2 spi_cs# m1 aio[0] c4 mic_rp c7 mic_ln a11 mic_rn c8 pio[9] / nc l10 pio[8] / nc l8 pio[11] l9 pio[13] j10 pio[12] k10 pio[14] m7 pio[10] m8 vdd_pads_2 k7 vss_audio c9 mic_bias_a a9 au_ref b9 vss_audio_drv b6 spkr_rn a7 spkr_rp b7 spkr_ln c6 spkr_lp c5 vregenable e10 vchg g12 chg_ext f11 vbat_sense h11 vbat h12 lx_1v8 j12 bypass reg charger po[30] / led[1] k5 po[29] / led[0] k4 po[31] / led[2] m4 mic bias spi_clk e1 pio[17] / pcm_in f1 pio[18] / pcm_out h3 usb_p m9 usb_n m10 vss_smps_1v8 j11 vdd_eflash_1v8 j1 nc k2 nc j2 nc j3 mic_bias_b b8 mic bias nc f6 1v8 smps 1v35 smps vss_smps_1v35 m12 nc g6 nc h1 nc g1 cap_sense_5 f2 cap_sense_4 f3 cap_sense_3 e3 cap_sense_2 e2 cap_sense_1 d3 cap_sense_0 d2 vdd_audio a8 vdd_bt_radio a5 vdd_ana c2 vdd_aux c3 aux ldo ana ldo 1v35 1v35 (optional) lx_1v35 l12 smps_1v35_sense m11 vdd_aux_1v8 a1 1v35 vdd_bt_lo a2 vdd_dig_eflash e12 dig ldo 0v85 - 1v20 vregin_dig e11 pio[15] l6 pio[25] / qspi_flash_io0 c11 pio[26] / qspi_flash_io1 b11 pio[27] / qspi_flash_io2 c10 pio[28] / qspi_flash_io3 d12 pio[23] / qspi_flash_cs# d11 pio[21] / qspi_flash_clk c12 vdd_pads_3 a12 vss_dig g10 vss_dig g7 smps_3v3 k11 smp_vbat k12 vdd_usb l11 vdd_audio_drv a6 nc b4 nc b3 vss_bt_radio b5 vss_dig f7 vss_dig d10 vss_dig h10 pio[24] / qspi_sram_cs# b10 pio[22] / qspi_sram_clk b12 smps_1v8_sense f10 vchg g11 psu_enables 1v8_ext 100n c9 leds aios capacitive touch sensors spi pcm / i2s / spdif uart pios serial flash / sram 16r / 32r 16r / 32r t h g i r t f e l 15nh l1 15p c15 2u2 c10 mic b mic a 15nh l2 15p c16 100n c11 2k2 r1 100n c12 100n c13 100n c14 2k2 r2 100n c7 vchg and vbat must be connected to gnd connect 1v8_ext to vout_3v3. this powers internal references if using rst# connect rst# (l1) and vregenable (e10) resetb together. otherwise leave rst# as nc and tie vregenable resetb to 1v8_ext. 1v8_ext 1v8_ext 1v8_ext resetb figure 14.1: external 1.8v supply example application production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 82 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0008746.1.1 3v3_ext out 2 in 4 gnd 1 gnd 3 2.45ghz u2 26mhz x1 bt rx / tx r 0 5 r 0 5 if using rst# connect rst# (l1) and vregenable (e10) 2u2 c1 resetb together. otherwise leave rst# as nc and tie vregenable resetb resetb leds aios capacitive touch sensors spi pcm / i2s / spdif uart pios serial flash / sram 2u2 c2 4u7 l1 1v8_smps 470n c10 100n c3 1v8_smps 4u7 c6 4u7 l2 1v35_smps 10n c4 10n c5 to 3v3_ext. 16r / 32r 16r / 32r t h g i r t f e l 15nh l3 15p c16 2u2 c11 mic b mic a 15nh l4 15p c17 100n c12 2k2 r1 100n c13 100n c14 100n c15 2k2 r2 vout_3v3 f12 vdd_pads_1 k1 vss_bt_lo_aux b2 vss_bt_radio a4 uart_cts l3 uart_rx m2 pio[16] / uart_rts k3 uart_tx m3 pio[5] l7 pio[2] m5 pio[6] m6 pio[1] l5 pio[4] k8 pio[19] / pcm_sync h2 pio[20] / pcm_clk g2 pio[7] k9 rst# l1 pio[3] k6 xtal_in c1 mic_lp a10 bt_rf a3 CSR8670 bga xtal_out b1 pio[0] l4 aio[1] d1 spi_mosi g3 spi_miso l2 spi_cs# m1 aio[0] c4 mic_rp c7 mic_ln a11 mic_rn c8 pio[9] / nc l10 pio[8] / nc l8 pio[11] l9 pio[13] j10 pio[12] k10 pio[14] m7 pio[10] m8 vdd_pads_2 k7 vss_audio c9 mic_bias_a a9 au_ref b9 vss_audio_drv b6 spkr_rn a7 spkr_rp b7 spkr_ln c6 spkr_lp c5 vregenable e10 vchg g12 chg_ext f11 vbat_sense h11 vbat h12 lx_1v8 j12 bypass reg charger po[30] / led[1] k5 po[29] / led[0] k4 po[31] / led[2] m4 mic bias spi_clk e1 pio[17] / pcm_in f1 pio[18] / pcm_out h3 usb_p m9 usb_n m10 vss_smps_1v8 j11 vdd_eflash_1v8 j1 nc k2 nc j2 nc j3 mic_bias_b b8 mic bias nc f6 1v8 smps 1v35 smps vss_smps_1v35 m12 nc g6 nc h1 nc g1 cap_sense_5 f2 cap_sense_4 f3 cap_sense_3 e3 cap_sense_2 e2 cap_sense_1 d3 cap_sense_0 d2 vdd_audio a8 vdd_bt_radio a5 vdd_ana c2 vdd_aux c3 aux ldo ana ldo 1v35 1v35 (optional) lx_1v35 l12 smps_1v35_sense m11 vdd_aux_1v8 a1 1v35 vdd_bt_lo a2 vdd_dig_eflash e12 dig ldo 0v85 - 1v20 vregin_dig e11 pio[15] l6 pio[25] / qspi_flash_io0 c11 pio[26] / qspi_flash_io1 b11 pio[27] / qspi_flash_io2 c10 pio[28] / qspi_flash_io3 d12 pio[23] / qspi_flash_cs# d11 pio[21] / qspi_flash_clk c12 vdd_pads_3 a12 vss_dig g10 vss_dig g7 smps_3v3 k11 smp_vbat k12 vdd_usb l11 vdd_audio_drv a6 nc b4 nc b3 vss_bt_radio b5 vss_dig f7 vss_dig d10 vss_dig h10 pio[24] / qspi_sram_cs# b10 pio[22] / qspi_sram_clk b12 smps_1v8_sense f10 vchg g11 15p c8 2u2 c7 10n c9 if using usb please refer to application note figure 14.2: external 3.3v supply example application production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 83 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
g-tw-0008747.1.1 2u2 c3 4u7 l1 vbus 3v3_usb 1v8_smps spi programming usb 470n c9 100n c4 2u2 c2 1v8_smps 2u2 c1 15p c7 2u2 c8 470n c6 1v35_ana 10n c5 3v3_usb out 2 in 4 gnd 1 gnd 3 2.45ghz u2 26mhz x1 1v8_smps 330r r1 red d1 vbus gnd 5 id 4 d+ 3 d- 2 vbus 1 gnd 6 gnd 7 usb mini-b con1 usb interface usb_p usb_n 8kv esd protection on chip c1 is required for 8kv esd protection. please follow routing guidelines. optional led & debug port bt rx / tx r 0 5 r 0 5 use smps dual mode if driving low impedance audio and change pskey_ana_reg_user nf c10 c10 is optional ana ldo requires 2.2uf on its input. this is shared with if using smps CSR8670 assumes h12 and k12 are at the same voltage and f12 and k11 are at the same voltage if using audio connect 2.2uf required for ana ldo smps_sense_1v35 must be connected to gnd vdd_audio (a8) to 1v35_ana, if using rst# connect rst# (l1) and vregenable (e10) together vdd_audio_drv (a6) to 1v8_smps turn off 1v35 smps in pskey vout_3v3 f12 vdd_pads_1 k1 vss_bt_lo_aux b2 vss_bt_radio a4 uart_cts l3 uart_rx m2 pio[16] / uart_rts k3 uart_tx m3 pio[5] l7 pio[2] m5 pio[6] m6 pio[1] l5 pio[4] k8 pio[19] / pcm_sync h2 pio[20] / pcm_clk g2 pio[7] k9 rst# l1 pio[3] k6 xtal_in c1 mic_lp a10 bt_rf a3 CSR8670 bga xtal_out b1 pio[0] l4 aio[1] d1 spi_mosi g3 spi_miso l2 spi_cs# m1 aio[0] c4 mic_rp c7 mic_ln a11 mic_rn c8 pio[9] / nc l10 pio[8] / nc l8 pio[11] l9 pio[13] j10 pio[12] k10 pio[14] m7 pio[10] m8 vdd_pads_2 k7 vss_audio c9 mic_bias_a a9 au_ref b9 vss_audio_drv b6 spkr_rn a7 spkr_rp b7 spkr_ln c6 spkr_lp c5 vregenable e10 vchg g12 chg_ext f11 vbat_sense h11 vbat h12 lx_1v8 j12 bypass reg charger po[30] / led[1] k5 po[29] / led[0] k4 po[31] / led[2] m4 mic bias spi_clk e1 pio[17] / pcm_in f1 pio[18] / pcm_out h3 usb_p m9 usb_n m10 vss_smps_1v8 j11 vdd_eflash_1v8 j1 nc k2 nc j2 nc j3 mic_bias_b b8 mic bias nc f6 1v8 smps 1v35 smps vss_smps_1v35 m12 nc g6 nc h1 nc g1 cap_sense_5 f2 cap_sense_4 f3 cap_sense_3 e3 cap_sense_2 e2 cap_sense_1 d3 cap_sense_0 d2 vdd_audio a8 vdd_bt_radio a5 vdd_ana c2 vdd_aux c3 aux ldo ana ldo 1v35 1v35 (optional) lx_1v35 l12 smps_1v35_sense m11 vdd_aux_1v8 a1 1v35 vdd_bt_lo a2 vdd_dig_eflash e12 dig ldo 0v85 - 1v20 vregin_dig e11 pio[15] l6 pio[25] / qspi_flash_io0 c11 pio[26] / qspi_flash_io1 b11 pio[27] / qspi_flash_io2 c10 pio[28] / qspi_flash_io3 d12 pio[23] / qspi_flash_cs# d11 pio[21] / qspi_flash_clk c12 vdd_pads_3 a12 vss_dig g10 vss_dig g7 smps_3v3 k11 smp_vbat k12 vdd_usb l11 vdd_audio_drv a6 nc b4 nc b3 vss_bt_radio b5 vss_dig f7 vss_dig d10 vss_dig h10 pio[24] / qspi_sram_cs# b10 pio[22] / qspi_sram_clk b12 smps_1v8_sense f10 vchg g11 smps 2.2uf (c3) psu_enables 3v3_usb figure 14.3: usb dongle example application production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 84 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
15 electrical characteristics 15.1 absolute maximum ratings rating min max unit storage temperature -40 105 c supply voltage 5v (usb vbus) vchg -0.4 5.75 v 3.3v smps_3v3 -0.4 3.60 v vdd_usb -0.4 3.60 v battery led[2:0] -0.4 4.40 v smp_vbat -0.4 4.40 v vbat_sense -0.4 5.75 v vregenable -0.4 4.40 v 1.8v vdd_audio_drv -0.4 1.95 v vdd_aux_1v8 -0.4 1.95 v vdd_pads_1 -0.4 3.60 v vdd_pads_2 -0.4 3.60 v vdd_pads_3 -0.4 3.60 v smps_1v8_sense -0.4 1.95 v 1.35v smps_1v35_sense -0.4 1.45 v vdd_audio -0.4 1.45 v vregin_dig -0.4 1.95 v other terminal voltages vss - 0.4 vdd + 0.4 v production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 85 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
15.2 recommended op erating conditions rating min typ max unit operating temperature range -40 20 85 c supply voltage 5v (usb vbus) vchg (a) 4.75 / 3.10 5.00 5.75 v 3.3v smps_3v3 3.10 3.30 3.60 v vdd_usb 3.10 3.30 3.60 v battery led[2:0] 1.10 3.70 4.25 v smp_vbat 2.50 3.70 4.25 v vbat_sense 0 3.70 4.25 v vregenable 0 3.70 4.25 v 1.8v vdd_audio_drv 1.70 1.80 1.95 v vdd_aux_1v8 1.70 1.80 1.95 v vdd_pads_1 1.70 1.80 3.60 v vdd_pads_2 1.70 1.80 3.60 v vdd_pads_3 1.70 1.80 3.60 v smps_1v8_sense 1.70 1.80 1.95 v 1.35v smps_1v35_sense 1.30 1.35 1.40 v vdd_audio 1.30 1.35 1.40 v vregin_dig 1.30 1.35 or 1.80 1.95 v (a) reduced specification from 3.1v to 4.75v. full specification >4 .75v. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 86 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
15.3 input/output terminal characteristics note: for all i/o terminal characteristics: current drawn into a pin is defined as positive; current suppli ed out of a pin is defined as negative. 15.3.1 regulators: available for external use 15.3.1.1 1.8v switch-mode regulator 1.8v switch-mode regulator min typ max unit input voltage 2.80 3.70 4.25 v output voltage 1.70 1.80 1.90 v normal operation transient settling time - 30 - s load current - - 185 ma current available for external use, stereo audio with 16 load (a) - - 25 ma peak conversion efficiency (b) - 90 - % switching frequency 3.63 4.00 4.00 mhz inductor saturation cu rrent, stereo and 16 load 250 - - ma inductor esr 0.1 0.3 0.8 low-power mode, automatically entered in deep sleep transient settling time - 200 - s load current 0.005 - 5 ma current available for external use - - 5 ma peak conversion efficiency - 85 - % switching frequency 100 - 200 khz (a) more current available for audio loads above 16. (b) conversion efficiency depends on inductor selection. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 87 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
15.3.1.2 combined 1.8v and 1.35v switch-mode regulator combined 1.8v and 1.35v switch-mode regulator min typ max unit input voltage 2.80 3.70 4.25 v output voltage 1.70 1.80 1.90 v normal operation transient settling time - 30 - s load current - - 340 ma current available for external use, stereo audio with 16 load (a) - - 25 ma peak conversion efficiency (b) - 90 - % switching frequency 3.63 4.00 4.00 mhz inductor saturation cu rrent, stereo and 16 load 400 - - ma inductor esr 0.1 0.3 0.8 low-power mode, automatically entered in deep sleep transient settling time - 200 - s load current 0.005 - 5 ma current available for external use - - 5 ma peak conversion efficiency - 85 - % switching frequency 100 - 200 khz (a) more current available for audio loads above 16. (b) conversion efficiency depends on inductor selection. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 88 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
15.3.1.3 bypass ldo regulator normal operation min typ max unit input voltage (a) 4.75 / 3.1 5.00 5.75 v output voltage (v in > 4.25v) 3.20 3.30 3.40 v output current (v in > 4.75v) - - 250 ma (a) minimum input voltage of 4.75v is required for full specificati on, regulator operates at reduced load current from 3.1v. 15.3.2 regulators: for internal use only 15.3.2.1 1.35v switch-mode regulator 1.35v switch-mode regulator min typ max unit input voltage 2.80 3.70 4.25 v output voltage 1.30 1.35 1.40 v normal operation transient settling time - 30 - s load current - - 160 ma current available for external use, stereo audio with 16 load - - 0 ma peak conversion efficiency (a) - 88 - % switching frequency 3.63 4.00 4.00 mhz inductor saturation cu rrent, stereo and 16 load 220 - - ma inductor esr 0.1 0.3 0.8 low-power mode, automatically entered in deep sleep transient settling time - 200 - s load current 0.005 - 5 ma current available for external use - - 0 ma peak conversion efficiency - - 85 % switching frequency 100 - 200 khz (a) conversion efficiency depends on inductor selection. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 89 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
15.3.2.2 low-voltage vdd_dig linear regulator normal operation min typ max unit input voltage 1.30 1.35 or 1.80 1.95 v output voltage (a) 0.80 0.90 / 1.20 1.25 v internal load current - - 80 ma (a) output voltage level is software controlled 15.3.2.3 low-voltage vdd_aux linear regulator normal operation min typ max unit input voltage 1.70 1.80 1.95 v output voltage 1.30 1.35 1.45 v internal load current - - 5 ma 15.3.2.4 low-voltage vdd_ana linear regulator normal operation min typ max unit input voltage 1.70 1.80 1.95 v output voltage 1.30 1.35 1.45 v load current - - 60 ma 15.3.3 regulator enable vregenable, switching threshold min typ max unit rising threshold 1.0 - - v 15.3.4 battery charger battery charger min typ max unit input voltage, vchg (a) 4.75 / 3.10 5.00 5.75 v (a) reduced specification from 3.1v to 4.75v. full specification >4 .75v. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 90 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
trickle charge mode min typ max unit charge current i trickle , as percentage of fast charge current 8 10 12 % v fast rising threshold - 2.9 - v v fast rising threshold trim step size - 0.1 - v v fast falling threshold - 2.8 - v fast charge mode min typ max unit charge current during constant current mode, i fast max, headroom > 0.55v 194 200 206 ma min, headroom > 0.55v - 10 - ma reduced headroom charge current, as a percentage of i fast mid, headroom = 0.15v 50 - 100 % i-ctrl charge current step size - 10 - ma v float threshold, calibrated 4.16 4.20 4.24 v standy mode min typ max unit voltage hysteresis on vbat, v hyst 100 - 150 mv error charge mode min typ max unit headroom (a) error rising threshold 30 - 50 mv headroom (a) error threshold hysteresis 20 - 30 mv (a) headroom = vchg - vbat external charge mode (a) min typ max unit fast charge current, i fast 200 - 500 ma control current into chg_ext 0 - 20 ma voltage on chg_ext 0 - 5.75 v external pass device h fe - 50 - - sense voltage, between vbat_sense and vbat at maximum current 195 200 205 mv (a) in the external mode, the battery charger meets all the previou s charger electrical characteristics and the additional or supe rseded electrical characteristics are listed in this table. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 91 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
15.3.5 reset power-on reset min typ max unit vdd_dig falling threshold (active mode) - 0.97 - v vdd_dig rising threshold (active mode) - 1.10 - v vdd_dig hysteresis (active mode) - 130 - mv vdd_dig falling threshold (deep sleep mode) - 0.77 - v vdd_aux_1v8 falling threshold (a) - 1.46 - v vdd_aux_1v8 rising threshold - 1.65 - v vdd_aux_1v8 hysteresis - 190 - mv (a) the 1.8v switch-mode power suppl y rail can briefly drop to >1.3 v during deep sleep exit. this is expected behaviour and does n ot cause a reset. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 92 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
15.3.6 usb min typ max unit vdd_usb for correct usb operation 3.10 3.30 3.60 v input threshold v il input logic level low - - 0.30 x vdd_usb v v ih input logic level high 0.70 x vdd_usb - - v input leakage current vss_dig < v in < vdd_usb (a) -1 1 5 a c i input capacitance 2.5 - 10 pf output voltage levels to correctly terminated usb cable v ol output logic level low 0 - 0.2 v v oh output logic level high 2.80 - vdd_usb v (a) internal usb pull-up disabled 15.3.7 clocks crystal oscillator min typ max unit frequency 19.2 26 42 mhz crystal load capacitance (a) - 0 - pf frequency stability - - 20 ppm frequency tolerance - - 10 ppm transconductance 2 - - ms (a) load capacitors integral to CSR8670 bga production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 93 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
external clock min typ max unit input frequency (a) 19.2 26 42 mhz clock input level (b) 0.2 0.4 vdd_aux v pk-pk edge jitter (allowable jitter), at zero crossing - - 10 ps rms xtal_in input impedance 30 - - k xtal_in input capacitance - - 1 pf dc level -0.4 - vdd_aux + 0.4 v (a) clock input is any frequency from 19.2mhz to 42mhz in steps of 250khz plus cdma/3g tcxo frequencies of 19.2, 19.44, 19.68, 19. 8 and 38.4mhz. (b) clock input is either sinusoida l or square wave . if the peaks o f the signal are below vss_bt_lo_ aux or above vdd_aux. a dc blo cking capacitor is required betwe en the signal and xtal_in. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 94 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
15.3.8 stereo codec: analogue to digital converter analogue to digital converter parameter conditions min typ max unit resolution - - - 16 bits input sample rate, f sample - 8 - 48 khz snr f in = 1khz b/w = 20hzf sample /2 (20khz max) a-weighted thd+n < 0.1% 1.6v pk-pk input f sample 8khz - 93 - db 16khz - 92 - db 32khz - 92 - db 44.1khz - 92 - db 48khz - 92 - db thd+n f in = 1khz b/w = 20hzf sample /2 (20khz max) 1.6v pk-pk input f sample 8khz - 0.004 - % 48khz - 0.008 - % digital gain digital gain resolution = 1/32 -24 - 21.5 db analogue gain pre-amplifier setting = 0db, 9db, 21db or 30db analogue setting = -3db to 12db in 3db steps -3 - 42 db stereo separation (crosstalk) - -89 - db production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 95 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
15.3.9 stereo codec: digital to analogue converter digital to analogue converter parameter conditions min typ max unit resolution - - - 16 bits output sample rate, f sample - 8 - 96 khz snr f in = 1khz b/w = 20hz20khz a-weighted thd+n < 0.01% 0dbfs input f sample load 48khz 100k - 96 - db 48khz 32 - 96 - db 48khz 16 - 96 - db thd+n f in = 1khz b/w = 20hz20khz 0dbfs input f sample load 8khz 100k - 0.002 - % 8khz 32 - 0.002 - % 8khz 16 - 0.003 - % 48khz 100k - 0.003 - % 48khz 32 - 0.003 - % 48khz 16 - 0.004 - % digital gain digital gain resolution = 1/32 -24 - 21.5 db analogue gain analogue gain resolution = 3db -21 - 0 db stereo separation (crosstalk) - -88 - db production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 96 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
15.3.10 digital digital terminals min typ max unit input voltage v il input logic level low -0.4 - 0.4 v v ih input logic level high 0.7 x vdd - vdd + 0.4 v tr/tf - - 25 ns output voltage v ol output logic level low, l ol = 4.0ma - - 0.4 v v oh output logic level high, l oh = -4.0ma 0.75 x vdd - - v tr/tf - - 5 ns input and tristate currents strong pull-up -150 -40 -10 a strong pull-down 10 40 150 a weak pull-up -5 -1.0 -0.33 a weak pull-down 0.33 1.0 5.0 a c i input capacitance 1.0 - 5.0 pf 15.3.11 led driver pads led driver pads min typ max unit current, i pad high impedance state - - 5 a current sink state - - 10 ma led pad voltage, v pad i pad = 10ma - - 0.55 v led pad resistance v pad < 0.5v - - 40 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 97 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
15.3.12 auxiliary adc auxiliary adc min typ max unit resolution - - 10 bits input voltage range (a) 0 - vdd_aux v accuracy (guaranteed monotonic) inl -1 - 1 lsb dnl 0 - 1 lsb offset -1 - 1 lsb gain error -0.8 - 0.8 % input bandwidth - 100 - khz conversion time 1.38 1.69 2.75 s sample rate (b) - - 700 samples/s (a) lsb size = vdd_aux/1023 (b) the auxiliary adc is accessed thr ough a vm function. the sample rate given is achieved as part of this function. 15.3.13 auxiliary dac auxiliary dac min typ max unit resolution - - 10 bits supply voltage, vdd_dac 1.30 1.35 1.40 v output voltage range 0 - vdd_aux v full-scale output voltage 1.30 1.35 1.40 v lsb size 0 1.32 2.64 mv offset -1.32 0 1.32 mv integral non-linearity -1 0 1 lsb settling time (a) - - 250 ns (a) the settling time does not i nclude any capacitive load production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 98 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
15.4 esd protection apply esd static handling precautions during manufacturing. table 15.1 shows the esd handling maximum ratings. condition class max rating human body model contact discharge per jedec eia/jesd22?a114 2 2kv (all pins except chg_ext, smps_1v35_sense and smps_1v8_sense at 1kv) machine model contact discharge per jedec eia/jesd22?a115 200v 200v (all pins except chg_ext at 100v) charged device model contact discharge per jedec eia/jesd22?c101 ii 200v (all pins) table 15.1: esd handling ratings production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 99 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
16 power consumption dut role connection packet type average current unit n/a deep sleep with uart host connection - 55 a n/a page scan page = 1280ms interval window = 11.25ms - 219 a n/a inquiry and page scan inquiry = 1280ms interval page = 1280ms interval window = 11.25ms - 378 a master acl sniff = 500ms, 1 attempt, 0 timeout dh1 119 a master acl sniff = 1280ms, 8 attempts, 1 timeout dh1 109 a master sco sniff = 100ms, 1 attempt, pcm hv3 7.6 ma master sco sniff = 100ms, 1 attempt, mono audio codec hv3 9.8 ma master esco setting s3, sniff = 100ms, pcm 2ev3 5.8 ma master esco setting s3, sniff = 100ms, pcm 3ev3 5.4 ma master esco setting s3, sniff = 100ms, mono audio codec 2ev3 7.9 ma master esco setting s3, sniff = 100ms, mono audio codec 3ev3 7.5 ma slave acl sniff = 500ms, 1 attempt, 0 timeout dh1 127 a slave acl sniff = 1280ms, 8 attempts, 1 timeout dh1 129 a slave sco sniff = 100ms, 1 attempt, pcm hv3 7.8 ma slave sco sniff = 100ms, 1 attempt, mono audio codec hv3 10 ma slave esco setting s3, sniff = 100ms, pcm 2ev3 6.2 ma slave esco setting s3, sniff = 100ms, pcm 3ev3 5.8 ma slave esco setting s3, sniff = 100ms, mono audio codec 2ev3 8.2 ma slave esco setting s3, sniff = 100ms, mono audio codec 3ev3 7.9 ma production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 100 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
note: current consumption values are taken with: vbat pin = 3.7v firmware id = 7919 rf tx power set to 0dbm no rf retransmissions in case of esco audio gateway transmits silence when sco/esco channel is open leds disconnected afh off production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 101 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
17 csr green semiconductor pr oducts and rohs compliance csr confirms that csr green semi conductor products comply with the following regulatory requirements: restriction on hazardous substances directive guidelines in the eu rohs directive 2002/95/ec. this includes compliance with the requirements for deca bde, as per removal of exemption, implementation date 01-jul-08 eu reach, regulation (ec) no 1907/2006: list of substances subject to authorisation (annex xiv) restrictions on the manufacture, placing on the market and use of certain dangerous substances, preparations and articles (annex xvii). this annex now includes requirements that were contained within eu directive, 76/769/eec. there are many substance restr ictions within this annex, including, but not limited to, the control of use of perfluorooctane sulfo nates (pfos). substances identified on candidate list as substances of very h igh concern (svhc), 46 substances as per update published 15 december 2010. eu commission decision 2009/251/ec: products containing dimethylfumarate (dmf) are not placed or ma de available on the market. eu packaging and packaging waste, directive 94/62/ec montreal protocol on substances that deplete the ozone layer additionally, table 17.1 shows that csr green semiconductor pro ducts are free from bromi ne, chlorine or antimony trioxide and other hazardous chemicals. material maximum allowable amount cadmium (cd) 100ppm lead (pb) 1000ppm (solder), 100pm (plastic) mercury (hg) 1000ppm hexavalent-chromium (cr vi) 1000ppm polybrominated biphenyls (pbb) 1000ppm polybrominated diphenyl ethers (pbde) 1000ppm bromine, chlorine 900ppm, <1500ppm combined antimony trioxide (sb 2 o 3 ) 900ppm benzene 1000ppm beryllium and compounds (other than beryllium oxide (beo) 1000ppm halogenated diphenyl methanes (monomethyltetrachloro diphenyl methane (cas# 76253-60-6), monomethyldichloro diphenyl methane (cas# 81161-70-8), monomethyldibromo diphenyl methane (cas# 99788-47-8) 1000ppm red phosphorous 1000ppm 1,1,1-trichloroethane banned production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 102 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
material maximum allowable amount aliphatic chcs (chlorohydrocarbons) banned benzotriazole (2-3',5'-di-tert-butyl-2'-hydroxyphenyl) banned beryllium oxide banned chlorinated paraffin (includi ng short chain chlorinated paraffi ns C carbon chain length 10-13 and medium c hain chlorinated paraffins C car bon chain length 14-17) banned formaldehyde (banned in wooden, adhesive and plastic products) banned as described hydrofluorocarbon (hfc) banned nps (nonylphenols) and npes (nonylphenol ethoxylates) (banned in textile, leather, metal, pulp and paper parts) banned as described organic tin compounds banned perfluorocarbon (pfc) banned polychlorinated napthalenes (pcn) banned polychlorinated terphenyls (pct) banned polychlorinated biphenyls (pcb) banned polyvinyl chloride (pvc) banned sulfur hexafluoride banned tetrachloromethane (cas# 56-23-5) banned asbestos banned as intentionally introduced phthalates banned as intentionally introduced radioactive substances banned as intentionally introduced: reportable tributyl tin (tbt) / triphenyl ti n (tpt) / tributyl tin oxide ( tbto) dibutyl tin (dbt) and dioctyl tin compounds (dot) banned as intentionally introduced table 17.1: chemical limits for green semiconductor products products and shipment packaging are marked and labelled with ap plicable environmental marking symbols in accordance with relevant regulatory requirements. csr has defined this green standard based on current regulatory and customer requirements. for more information contact product.compliance@csr.com . production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 103 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
18 software CSR8670 bga: is supplied with on-chip bluetooth v3.0 specification qualified hci stack firmware has on-chip software that can be loaded with applications from csr's audio development kit, see section 18.2.1.1 has on-chip software that can be loaded with applications from csr's extension program 18.1 on-chip software 18.1.1 stand-alone CSR8670 bga and kalimba dsp applications figure 18.1 shows the structure of the stack for running on-chi p software and applications, it is built on top of the hci stack in section 18.1.2. the stack firmware requires no hos t processor, but uses a host processor for debugging etc, as figure 18.1 shows. the software layers for the applicat ion software run on the internal mcu in a protected user-software execution environment known as a vm and the dsp a pplication code runs from the dsp program memory ram. g-tw-0005532.2.2 lc program memory 56kb ram baseband mcu host i/o radio digital audio usb uart host for debugging and programming rfcomm sdp vm application software dsp application dsp control dm1 dm2 pm internal mcu kalimba dsp pcm / spdif / i 2 s digital microphones analogue audio lm l2cap hci microphones speakers figure 18.1: stand-alone CSR8670 bga and kalimba dsp applicatio ns note: program memory in figure 18.1 is internal flash. csr provides a development kit that customers can configure to meet their audio and consumer end-product requirements. the development kit include firmware components, applications a nd appropriate profile support. for more information see section 18.2.1. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 104 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
18.1.2 bluecore hci stack figure 18.2 shows hci stack implementation. the internal mcu ru ns the bluetooth stack up to the hci. g-tw-0006097.1.1 hci lm lc program memory 56kb ram bluetooth stack mcu host i/o radio digital audio host for debugging and programming analogue audio microphones usb uart pcm / spdif / i 2 s digital microphones speakers figure 18.2: bluecore hci stack note: program memory in figure 18.2 is internal flash. 18.1.2.1 latest features of the hci stack CSR8670 bga is qualified to the bluetooth v3.0 specification. 18.2 off-chip software 18.2.1 CSR8670 development kit csr's audio development kit for the CSR8670 bga, order code dk? 8670?10060?1a, includes a CSR8670 demonstrator board and necessary interface adapters and cables are available. in conjunction with the CSR8670 configurator tool and other supporting utilities the developmen t kit provides the best environment for designing audio solutions with the CSR8670 bga. important note: the CSR8670 audio development kit is subject to change and upda tes, for up-to-date information see www.csrsupport.com . production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 105 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
18.2.1.1 audio development kit software in conjunction with the CSR8670 audio development kit, software is available, it requires a bluetooth developer's licence to use. csrs current software includes: bluetooth profiles: bluetooth v3.0 specification support hfp v1.6 hsp v1.2 a2dp v1.2 avrcp v1.4 pbap v1.0 map v1.0 spp v1.0 improved audio quality: cvc 1-mic far-end audio enhancements (narrowband) cvc 2-mic far-end audio enhancements (narrowband) cvc 1-mic far-end audio enhancements (hands-free) cvc 1-mic far-end audio enhancements (wideband) cvc 2-mic far-end audio enhancements (wideband) cvc near-end audio enhancements plc / bec 1-mic wnr 2-mic wnr sidetone frequency expansion for improved speech intelligibility music enhancements: aptx codec technology 5-band eq 3d stereo separation dynamic range control faststream codec sbc decoder mp3 decoders aac and aac + decoders stereo ambient noise cancellation additional functionality: multipoint for hfp, a2dp and advance user-cases programmable audio prompts (compressed / sbc) support for capacitive touch control support for speech recognition support for multi-language programmable audio prompts csr's proximity pairing and csr's proximity connection multipoint support for hfp connection to 2 handsets for voice multipoint support for a2dp connection to 2 a2dp sources for mu sic playback talk-time extension 18.2.2 extension program support a wide range of software options i s available from csr's extens ion program support, see www.csr.com . production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 106 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
19 ordering information device package order number type size shipment method CSR8670 vfbga 112?ball (pb free) 6.5 x 6.5 x 1mm 0.5mm pitch tape and reel CSR8670c?ibbh?r note: minimum order quantity is 2kpcs taped and reeled. supply chain : csr's manufacturing policy is to multisource volume products. for further details, contact your local sales account manager or representative. to contact a csr representative, email sales@csr.com or go to www.csr.com/contacts . 19.1 CSR8670 development ki t ordering information description order number CSR8670 audio development kit dk?8670?10060?1a production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 107 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
20 tape and reel information for tape and reel packing and labelling see ic packing and labelling specification . 20.1 tape orientation figure 20.1 shows the general orientation of the CSR8670 bga pa ckage in the carrier tape. g-tw-0002434.3.2 circular holes user direction of feed b a a b pin a1 marker figure 20.1: tape orientation 20.2 tape dimensions figure 20.2 shows the dimensions of the tape for the CSR8670 bg a. g-tw-0005677.1.1 5 6.00 typ. 0.1 0.0 1.50 secti on a - a secti on b- b r0 . 5 0 (typ.) r0 . 3 0 (typ.) 0.0 0.1 1.50 16.00 0.3 7.50 se e n o t e 6 1.75 se e n o t e 1 4.00 ko k1 bo 6.00 typ. 0.30 0.05 12.00 ao a se e n o t e 6 2.00 b b a figure 20.2: tape dimensions production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 108 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
a 0 b 0 k 0 k 1 unit notes 6.80 6.80 1.60 1.10 mm 1. 10 sprocket hole pitch cumulative tolerance 0.2. 2. camber not to exceed 1mm in 100mm. 3. material: black polystyrene. 4. a 0 and b 0 measured on a plane 0.3mm above the bottom of the pocket. 5. k 0 measured from a plane on the inside bottom of the pocket to the top surface of the carrier tape. 6. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole 20.3 reel information g-tw-0000386.3.2 figure 20.3: reel dimensions production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 109 of 116 cs-127997-dsp2 www.csr.com data sheet free datasheet http://www.datasheetlist.com/
package type tape width a max b c d min n min w1 w2 max w3 units min max 6.5 x 6.5 x 1mm vfbga 16 332 1.5 13.0 (0.5/-0.2) 20.2 50 16.4 (3.0/-0.2) 19.1 16.4 19.1 mm 20.4 moisture se nsitivity level CSR8670 bga is qualified to moisture sensitivity level msl3 in accordance with jedec j-std-020. production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 110 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
21 document references document reference, date bluetest user guide cs-102736-ug bluetooth/ieee 802.11 b/g coexistence application note cs-207808-an bluetooth and usb design considerations cs-101412-an bluetooth specification version 3.0 + hs version 3.0 + hs [vol 0 to vol 5], 21 april 2009 configuring the power supplies on CSR8670 cs-204573-an configuring the touch sensor on CSR8670 cs-204575-an CSR8670 bga performance specification cs-203853-sp electrostatic discharge ( esd) sensitivity testing human body model (hbm) jesd22-a114f electrostatic discharge (esd) sensitivity testing, machine model (mm) jesd22-a115c field-induced charged-device model test method for electrostatic- discharge-withstand thresholds of microelectronic components jesd22-c101e ic packing and labelling specification cs-112584-sp kalimba architecture 3 dsp user guide cs-202067-ug lithium polymer battery charger calibration and operation for CSR8670 cs-204572-an moisture / reflow sensitivity classification for nonhermitic solid state surface mount devices ipc / jedec j-std-020 optimising bluecore5-multimedia adc performance application note cs-120059-an selection of i2c eeproms for use with bluecore bcore-an-008p typical solder reflow profile for lead-free device cs-116434-an universal serial b us specification v2.0, 27 april 2000 usb battery chargi ng specification v1.1, 15 april 2009 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 111 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
terms and definitions term definition 3g 3 rd generation of mobile communications technology -law audio companding standard (g.711) a-law audio companding standard (g.711) a2dp advanced audio distribution profile aac advanced audio coding ac alternating current acl asynchronous connection-oriented adc analogue to digital converter aes audio engineering society afc automatic frequency control afh adaptive frequency hopping agc automatic gain control alu arithmetic logic unit avrcp audio/video remote control profile bccmd bluecore command bcsp bluecore serial protocol bec bit error concealment bist built-in self-test bluetooth ? set of technologies providing audio and data transfer over shor t-range radio connections bmc burst mode controller cdma code division multiple access codec coder decoder crc cyclic redundancy check csr cambridge silicon radio cvc clear voice capture cvsd continuous variable slope delta modulation dac digital to analogue converter dc direct current production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 112 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
term definition dds direct digital synthesis dfu device firmware upgrade dma direct memory access dnl differential non linearity (adc accuracy parameter) dsp digital signal processor dut device under test e.g. exempli gratia , for example ebu european broadcasting union edr enhanced data rate eeprom electrically erasable programmable read only memory eia electronic industries alliance eq equaliser esco extended sco esd electrostatic discharge esr equivalent series resistance etc et cetera , and the rest, and so forth fir finite impulse response (filter) fsk frequency shift keying g.722 an itu-t standard wideband speech codec operating at 48, 56 and 64 kbps gci general circuit interface gsm global system for mobile communications h4ds h4 deep sleep hbm human body model hci host controller interface hfp hands-free profile hsp headset profile i2c inter-integra ted circuit interface i2s inter-integrated circuit sound i.e. id est , that is i/o input/output production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 113 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
term definition ic integrated circuit id identifier ieee institute of electronic and electrical engineers if intermediate frequency iir infinite impulse response (filter) inl integral non linearity (adc accuracy parameter) iq in-phase and quadrature isdn integrated services digital network jedec joint electron device engineering council (now the jedec solid state technology association) kalimba an open platform dsp co-processor, enabling support of enhanced audio applications, such as echo and noise suppression, and file compression / decompres sion kb kilobit lc an inductor (l) and ca pacitor (c ) network lcd liquid-crystal display ldo low (voltage) drop-out led light-emitting diode lm link manager lna low noise amplifier lsb least significant bit (or byte) mac multiplier and accumulator map message access profile mb megabit mcu microcontroller unit mems micro electro mechanical system mips million instructions per second miso master in slave out mlc multilayer ceramic mmu memory management unit mp3 mpeg-1 audio layer 3 n/a not applicable production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 114 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
term definition nc not connect nsmd non solder mask defined pa power amplifier pbap phonebook access profile pc personal computer pcb printed circuit board pcm pulse code modulation pd pull-down pio parallel input/output pio programmable input/output, also known as general purpose i/o plc packet loss concealment plc public limited company po programmable output ppm parts per million ps key persistent store key pu pull-up pwm pulse width modulation ram random access memory rc a resistor and capacitor network rca radio corporation of america, normally used to refer to a rca c onnector (also know as phono connector or cinch connector) rf radio frequency rgb red green blue risc reduced instruction set computer rohs restriction of hazardous substances in electrical and electroni c equipment directive (2002/95/ec) rs-232 recommended standard-232, a tia/eia standard for serial transmi ssion between computers and peripheral devices (modem, mouse, etc.) rssi received signal strength indication rts request to send rx receive or receiver sbc sub-band coding production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 115 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/
term definition sco synchronous connection-oriented sig (bluetooth) specia l interest group smps switch mode power supply snr signal-to-noise ratio soc system on-chip s/pdif sony/philips digital interface (also iec 958 type ii, part of i ec-60958). an interface designed to transfer stereo digital audio signals between various device s and stereo components with minimal loss. spi serial peripheral interface spp serial port profile sqif serial quad i/o flash (interface) sram static random access memory tbd to be defined tcxo temperature compensated crystal oscillator thd+n total harmonic distortion and noise tv television tx transmit or transmitter uart universal asynchronous receiver transmitter unity collective name for csrs bluetooth/wi-fi coexistence schemes unity+ csrs advanced coexistence scheme. extra signalling wire used i n conjunction with unity-3 or unity-3e for improved coexistence with periodic bluetooth ac tivity. unity-3 de facto industry standard 3-wire coexistence signalling scheme usb universal serial bus vco voltage controlled oscillator vfbga very thin, fine pitch, ball grid array vm virtual machine w-cdma wideband code division multiple access wlan wireless local area network wnr wind noise reduction production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2011 page 116 of 116 cs-127997-dsp2 www.csr.com CSR8670 bga data sheet free datasheet http://www.datasheetlist.com/

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